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FPGA Glossary

The terms that matter most in fpga development, with real-world context from FPGARelated's forums and blogs.

73 terms | The glossary grows by about 5 new entries per day.

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HDL & Languages
7 terms
Logic Resources
11 terms
Vendor Tools
6 terms
Architecture
6 terms
Timing & Analysis
6 terms
Configuration
7 terms
I/O & Clocking
13 terms
IP & Buses
4 terms
Verification
3 terms
Protocols
2 terms
DSP in FPGA
8 terms

All terms (A-Z)

A B C D F G H I J L M N O P R S T V W X
A
  • ASIC [architecture] An Application-Specific Integrated Circuit (ASIC) is an integrated circuit designed and fabricated for one specific application or function,...
  • AXI [ip-and-bus] AXI (Advanced eXtensible Interface), formally AXI4, is a high-performance on-chip bus protocol defined by ARM as part of the AMBA specificat...
B
  • Bitstream [configuration] A bitstream (sometimes called a bit file in certain vendor toolchains) is a binary configuration file that encodes the logic, routing, and m...
  • BRAM [logic-resources] Block RAM (BRAM) is a dedicated, hard-instantiated on-chip memory resource found in a wide range of FPGAs, distinct from logic fabric (LUTs/...
  • BUFG [io-and-clocking] A BUFG (Global Clock Buffer) is a dedicated high-fanout clock-driving primitive found in Xilinx FPGAs that connects a clock source to the de...
C
  • CIC Filter [dsp-in-fpga] A CIC (Cascaded Integrator-Comb) filter is a computationally efficient linear-phase filter used primarily for large-ratio sample rate conver...
  • CLB [logic-resources] A Configurable Logic Block (CLB) is the fundamental repeating logic cell in Xilinx FPGAs, consisting of lookup tables (LUTs), flip-flops, ca...
  • Clock Domain Crossing [timing] A clock domain crossing (CDC) occurs when a digital signal is generated in one clock domain and sampled in another, where the two clocks are...
  • Clock Enable [logic-resources] A clock enable (CE) is a synchronous control signal that gates the operation of a register, counter, or block of logic without gating the cl...
  • Clock Skew [timing] Clock skew is the difference in arrival time of the same clock edge at two or more points in a digital circuit, caused by differences in rou...
  • Combinational Logic [logic-resources] Combinational logic is digital logic in which the output at any moment depends only on the current inputs, with no internal state or memory ...
  • CPLD [architecture] A Complex Programmable Logic Device (CPLD) is a type of programmable logic chip that implements combinational and registered logic through a...
D
  • DDR Memory [protocols] DDR (Double Data Rate) SDRAM is a class of synchronous DRAM that transfers data on both the rising and falling edges of the clock, doubling ...
  • Decimator [dsp-in-fpga] A decimator is a digital signal processing block that reduces the sample rate of a signal by an integer factor M, typically preceded by a lo...
  • Distributed RAM [logic-resources] Distributed RAM is a feature of many SRAM-based FPGAs that allows the look-up tables (LUTs) normally used for logic to be reconfigured as sm...
  • DLL [io-and-clocking] A Delay-Locked Loop (DLL) is a closed-loop clock-conditioning circuit that uses a chain of delay elements and a feedback comparator to align...
  • Drive Strength [io-and-clocking] Drive strength is a configurable parameter on GPIO and other I/O pins that controls how much current the output driver can source or sink, w...
  • DSP Slice [dsp-in-fpga]
  • Duty Cycle [io-and-clocking] Duty cycle is the ratio of the active (high) time of a periodic signal to its total period, expressed as a percentage. A signal with a 25% d...
F
  • FFT [dsp-in-fpga]
  • FIFO [logic-resources] A FIFO (First-In First-Out) is a storage buffer in which data is read out in the same order it was written in. It is commonly used to decoup...
  • Finite State Machine [logic-resources] A finite state machine (FSM) is a computational model that describes a system as a fixed set of discrete states, a set of inputs, and define...
  • FIR Filter [dsp-in-fpga] A Finite Impulse Response (FIR) filter is a discrete-time linear filter whose output is computed as a weighted sum of a finite number of pas...
  • Flip-Flop [logic-resources] A flip-flop (FF) is a bistable sequential logic element that stores one bit of state, holding its output stable until a triggering event, mo...
  • Floating-Point (FPGA) [dsp-in-fpga]
  • FPGA [architecture] An FPGA (Field-Programmable Gate Array) is an integrated circuit containing a large array of configurable logic blocks (CLBs), programmable ...
G
  • Glitch [timing] A glitch is a spurious, unintended pulse or transient on a digital signal that occurs when combinational logic paths of different lengths ca...
H
  • Hardware Multiplier [dsp-in-fpga] A hardware multiplier is a dedicated digital logic block that computes the product of two binary operands in a fixed, small number of clock ...
  • HDL [hdl] A Hardware Description Language (HDL) is a specialized language used to describe the structure and behavior of digital circuits, enabling si...
  • HDL Simulation [verification] HDL simulation is the execution of a hardware description language (HDL) model -- written in VHDL, Verilog, SystemVerilog, or an HDL-like li...
  • HLS [hdl] High-Level Synthesis (HLS) is a design flow that compiles a behavioral description written in a high-level language (most commonly C, C++, o...
I
  • ICAP [configuration] The Internal Configuration Access Port (ICAP) is a vendor-specific primitive available on Xilinx FPGAs that provides fabric-side read and wr...
  • IDCODE [configuration] IDCODE is a mandatory JTAG register defined by IEEE 1149.1 that stores a 32-bit identification value identifying the manufacturer, part numb...
  • ILA [verification] An Integrated Logic Analyzer (ILA) is a soft-IP debug core instantiated inside an FPGA that captures internal signal activity into on-chip m...
  • IOB [io-and-clocking] An Input/Output Block (IOB) is a configurable I/O resource at the periphery of an FPGA that interfaces the internal fabric to a physical pac...
  • IOSTANDARD [io-and-clocking] IOSTANDARD is an attribute or constraint applied to FPGA I/O pins that selects the electrical signaling standard (voltage level, termination...
  • IP Core [ip-and-bus] An IP core (Intellectual Property core) is a reusable block of logic, described in HDL or delivered as a netlist or hard silicon block, that...
J
  • Jitter [timing] Jitter is the variation in the timing of a periodic signal or event relative to its ideal, expected position in time. It is measured as a de...
  • JTAG [configuration] JTAG (IEEE 1149.1, named after the Joint Test Action Group that created the standard) is a serial interface and protocol originally designed...
L
  • Latch [logic-resources] A latch is a level-sensitive bistable storage element that is transparent to its input while an enable signal is asserted, and holds its las...
  • LUT [logic-resources] A lookup table (LUT) is a small, configurable block of SRAM inside an FPGA or other programmable logic device that implements arbitrary comb...
  • LVDS [io-and-clocking] LVDS (Low-Voltage Differential Signaling) is a high-speed, low-power electrical signaling standard that transmits data as a small voltage di...
M
  • Memory Controller [ip-and-bus] A memory controller is a digital logic block, either integrated into an SoC/MCU or implemented as a discrete chip, that manages the electric...
  • Metastability [timing] Metastability is a condition in which a digital storage element (flip-flop, latch, or register) enters an indeterminate output state because...
  • MGT [io-and-clocking] A Multi-Gigabit Transceiver (MGT) is a high-speed serial I/O block integrated into an FPGA or ASIC that implements the physical layer (PHY) ...
  • MicroBlaze [architecture] MicroBlaze is a soft-core 32-bit RISC processor IP core developed by Xilinx (now AMD) and implemented in programmable logic on Xilinx FPGAs ...
  • MMCM [io-and-clocking] A Mixed-Mode Clock Manager (MMCM) is a clock synthesis and conditioning block found in certain Xilinx FPGA families that generates, multipli...
N
  • Netlist [vendor-tools] A netlist is a structural description of an electronic circuit that enumerates the circuit's components (cells, gates, or primitives) and th...
O
  • Oscillator [io-and-clocking] An oscillator is a circuit or device that produces a periodic signal, typically a square, sine, or clock waveform, without any external inpu...
P
  • Partial Reconfiguration [configuration] Partial reconfiguration (PR) is the ability to reprogram a defined region of an FPGA's programmable fabric while the rest of the device cont...
  • PHY [io-and-clocking] A PHY (Physical Layer) is a hardware block that implements the electrical, optical, or radio-frequency signaling required to transmit and re...
  • PLL [io-and-clocking] A Phase-Locked Loop (PLL) is a feedback control circuit that locks the phase (and therefore frequency) of an output signal to a reference si...
  • Processing Gain [dsp-in-fpga] Processing gain is the improvement in signal-to-noise ratio (SNR) achieved by specific signal processing operations -- most commonly filteri...
  • PROM [architecture] A PROM (Programmable Read-Only Memory) is a type of non-volatile memory that is manufactured blank and can be written exactly once by the us...
R
  • RLOC [configuration] RLOC (commonly expanded as Relative LOCation) is an FPGA placement constraint that specifies the position of a logic element relative to oth...
  • RTL [hdl] Register-Transfer Level (RTL) is an abstraction used in digital design that describes a circuit in terms of the flow of data between registe...
S
  • SDRAM [architecture] SDRAM (Synchronous DRAM) is a type of dynamic RAM that synchronizes its command and data transfers to an external clock signal, allowing the...
  • Signal Termination [io-and-clocking] Signal termination is the practice of placing a resistive (or reactive) load at the end of a transmission line to absorb signal energy and p...
  • Slice (FPGA) [logic-resources] A slice is the basic repeating logic unit inside the configurable logic blocks (CLBs) of Xilinx FPGAs, containing a fixed bundle of look-up ...
  • SPI [protocols] SPI (Serial Peripheral Interface) is a synchronous serial communication protocol that is typically full-duplex, using separate clock, data-o...
  • SVF [configuration] Serial Vector Format (SVF) is a plain-text file format that describes the JTAG operations needed to program or configure a device, expressed...
  • Synthesis (HDL) [vendor-tools] HDL synthesis is the process by which a hardware description language (HDL) source file -- written in VHDL, Verilog, or SystemVerilog -- is ...
  • SystemC [hdl]
  • SystemVerilog [hdl] SystemVerilog is a hardware description and verification language (HDVL) standardized as IEEE 1800 that extends Verilog with object-oriented...
T
  • TCL [vendor-tools] Tcl (Tool Command Language) is a dynamically typed scripting language originally created by John Ousterhout in 1988, designed to be easily e...
  • Testbench [verification] A testbench is a simulation environment or wrapper, written in an HDL or a verification language, that instantiates a design under test (DUT...
  • Timing Constraints [timing] Timing constraints are designer-supplied rules that tell an FPGA or ASIC implementation tool what timing requirements a design must meet, in...
V
  • Verilog [hdl] Verilog is a hardware description language (HDL) used to model, simulate, and synthesize digital logic, from individual gates up to complete...
  • VHDL [hdl] VHDL (VHSIC Hardware Description Language) is a strongly typed, concurrent hardware description language used to model, simulate, synthesize...
  • Vivado [vendor-tools] Vivado is Xilinx's (now AMD's) integrated design environment for FPGA and SoC development, targeting 7-series and newer device families (Art...
W
  • Wishbone Bus [ip-and-bus] Wishbone is an open, royalty-free on-chip interconnect specification originally developed by Silicore Corporation and now maintained by the ...
X
  • Xilinx EDK [vendor-tools] Xilinx EDK (Embedded Development Kit) was a suite of tools from Xilinx for designing, integrating, and debugging embedded processor systems ...
  • Xilinx ISE [vendor-tools] Xilinx ISE (Integrated Software Environment) is Xilinx's legacy FPGA/CPLD design suite, covering HDL entry, synthesis, implementation (mappi...