An Application-Specific Integrated Circuit (ASIC) is an integrated circuit designed and fabricated for one specific application or function, rather than as a general-purpose device. Unlike microcontrollers or FPGAs, an ASIC's logic is permanently fixed during the silicon manufacturing process.
In practice
ASICs appear in embedded systems as dedicated peripheral controllers, motor drivers, codec chips, power management ICs, and custom SoCs where a standard off-the-shelf part cannot meet cost, power, or performance targets at volume. Common examples include Ethernet PHYs, CAN transceivers, H-bridge drivers, and high-volume consumer SoCs such as those found in smartphones and IoT devices. From the embedded developer's perspective, an ASIC is typically a fixed-function component interfaced through SPI, I2C, UART, or a parallel bus, with behavior configured through registers rather than reprogrammed logic.
Designing a new ASIC from scratch is a major undertaking involving RTL design (commonly in Verilog or VHDL), synthesis, place-and-route, and silicon tape-out. Tape-out costs for modern process nodes can run from tens of thousands of dollars for older nodes (e.g., 180 nm) to tens of millions for sub-10 nm nodes, which makes ASICs economically justified primarily at high production volumes or where strict power and area constraints rule out alternatives. Structured ASICs and gate-array variants can reduce NRE (non-recurring engineering) cost somewhat, but still represent a significant commitment compared to an FPGA prototype.
A common embedded workflow is to prototype functionality in an FPGA first, then migrate the proven design to an ASIC for production. The VHDL or Verilog RTL used in the FPGA prototype is often reused or lightly adapted for the ASIC flow. Once fabricated, an ASIC cannot be field-updated; any logic bug requires a new tape-out, so thorough simulation and formal verification before tape-out are critical.
For most embedded projects that do not reach volumes justifying custom silicon, the practical interaction with ASICs is as a consumer: reading datasheets, writing register-level drivers, and integrating vendor-supplied application notes. Understanding that the chip's behavior is immutable -- no firmware update will ever change how the silicon itself computes -- is important when working around errata or limitations.
Frequently asked
What is the difference between an ASIC and an FPGA?
An
FPGA contains a fabric of configurable logic blocks that can be reprogrammed in the field by loading a new
bitstream. An ASIC has its logic permanently defined during silicon fabrication and cannot be changed afterward. FPGAs have higher per-unit cost and power consumption for equivalent logic density, but zero NRE cost and fast iteration. ASICs have high up-front NRE and tooling costs but offer lower per-unit cost, smaller die area, and better power efficiency at volume. A common path is to prototype in FPGA and tape out as an ASIC once the design is proven.
What is the difference between an ASIC and a microcontroller?
A microcontroller is itself often implemented as an ASIC, but it is a general-purpose programmable device: its behavior is changed by updating firmware, not by changing silicon. A custom ASIC is designed for one specific task; its logic is fixed at the time of manufacture. The two are not mutually exclusive -- a custom SoC can embed a CPU core (making it both a microcontroller and an ASIC), but the programmable CPU is just one block within the fixed silicon.
When does it make sense to develop a custom ASIC instead of using an off-the-shelf MCU or FPGA?
The primary drivers are volume, power, and area. At production quantities often cited in the range of tens of thousands to millions of units, the per-unit cost savings over an
FPGA can offset the NRE. Power-constrained applications (implantable medical devices, energy harvesting nodes) may require efficiency levels unreachable in a programmable device. Size
constraints in wearables or implants can also force custom silicon. For most embedded projects at lower volumes, an MCU or FPGA will be more economical.
What languages and tools are used to design an ASIC?
RTL design is most commonly done in
Verilog or
VHDL (see the EmbeddedRelated posts 'Learning VHDL - Basics' and 'An absolute position encoder VHDL core' for VHDL fundamentals applicable to both
FPGA and ASIC flows). The RTL is then synthesized using tools such as Synopsys Design Compiler or Cadence Genus, followed by place-and-route, timing closure, DRC/LVS checks, and final GDSII tape-out.
Simulation and formal verification tools are used throughout to catch bugs before the design is committed to silicon.
Can an ASIC contain a CPU core?
Yes. Many production ASICs embed one or more licensed CPU cores -- ARM Cortex-M or Cortex-A cores are common choices -- alongside custom logic blocks, forming a System-on-Chip (SoC). The CPU runs firmware stored in on-chip or external memory, while the surrounding fixed logic handles application-specific tasks such as signal processing, protocol offload, or power management. This is how most smartphone SoCs, smart-home chips, and purpose-built industrial SoCs are constructed.
Differentiators vs similar concepts
ASICs are often contrasted with FPGAs (field-programmable, reconfigurable, higher per-unit cost) and general-purpose MCUs/CPUs (software-programmable, fixed silicon but flexible behavior). A structured ASIC or gate-array sits between a full-custom ASIC and an
FPGA: it uses a pre-fabricated base layer to reduce NRE and lead time, but is still not field-reprogrammable. An ASSP (Application-Specific Standard Product) is an ASIC designed for a specific application domain but sold as a standard catalog part to multiple customers -- a CAN transceiver or Ethernet
PHY is an ASSP, not a fully custom ASIC.
