13 terms in this category.
B
-
BUFG
A BUFG (Global Clock Buffer) is a dedicated high-fanout clock-driving primitive found in Xilinx FPGAs that connects a clock source to the de...
D
-
DLL
A Delay-Locked Loop (DLL) is a closed-loop clock-conditioning circuit that uses a chain of delay elements and a feedback comparator to align...
-
Drive Strength
Drive strength is a configurable parameter on GPIO and other I/O pins that controls how much current the output driver can source or sink, w...
-
Duty Cycle
Duty cycle is the ratio of the active (high) time of a periodic signal to its total period, expressed as a percentage. A signal with a 25% d...
I
-
IOB
An Input/Output Block (IOB) is a configurable I/O resource at the periphery of an FPGA that interfaces the internal fabric to a physical pac...
-
IOSTANDARD
IOSTANDARD is an attribute or constraint applied to FPGA I/O pins that selects the electrical signaling standard (voltage level, termination...
L
-
LVDS
LVDS (Low-Voltage Differential Signaling) is a high-speed, low-power electrical signaling standard that transmits data as a small voltage di...
M
-
MGT
A Multi-Gigabit Transceiver (MGT) is a high-speed serial I/O block integrated into an FPGA or ASIC that implements the physical layer (PHY) ...
-
MMCM
A Mixed-Mode Clock Manager (MMCM) is a clock synthesis and conditioning block found in certain Xilinx FPGA families that generates, multipli...
O
-
Oscillator
An oscillator is a circuit or device that produces a periodic signal, typically a square, sine, or clock waveform, without any external inpu...
P
-
PHY
A PHY (Physical Layer) is a hardware block that implements the electrical, optical, or radio-frequency signaling required to transmit and re...
-
PLL
A Phase-Locked Loop (PLL) is a feedback control circuit that locks the phase (and therefore frequency) of an output signal to a reference si...
S
-
Signal Termination
Signal termination is the practice of placing a resistive (or reactive) load at the end of a transmission line to absorb signal energy and p...
