6 terms in this category.
C
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Clock Domain Crossing
A clock domain crossing (CDC) occurs when a digital signal is generated in one clock domain and sampled in another, where the two clocks are...
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Clock Skew
Clock skew is the difference in arrival time of the same clock edge at two or more points in a digital circuit, caused by differences in rou...
G
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Glitch
A glitch is a spurious, unintended pulse or transient on a digital signal that occurs when combinational logic paths of different lengths ca...
J
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Jitter
Jitter is the variation in the timing of a periodic signal or event relative to its ideal, expected position in time. It is measured as a de...
M
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Metastability
Metastability is a condition in which a digital storage element (flip-flop, latch, or register) enters an indeterminate output state because...
T
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Timing Constraints
Timing constraints are designer-supplied rules that tell an FPGA or ASIC implementation tool what timing requirements a design must meet, in...
