A CIC (Cascaded Integrator-Comb) filter is a computationally efficient linear-phase filter used primarily for large-ratio sample rate conversion (decimation or interpolation) in digital signal processing. Although the structure is equivalent to a linear-phase FIR filter in terms of its input-output response, it is implemented as a recursive (IIR-structured) cascade of integrators and comb sections rather than a direct FIR. It requires no multipliers -- only adders, subtractors, and delay elements -- making it well-suited for FPGA and ASIC implementations where hardware resources are constrained.
In practice
CIC filters appear most often in the receive path of sigma-delta ADCs and in software-defined radio (SDR) front-ends, where a high-rate 1-bit or low-bit-width bitstream must be decimated by a large factor (commonly 8 to 4096) before further processing. Because a CIC filter requires no multipliers, a decimating CIC can operate at the full input clock rate on an FPGA without consuming DSP slice resources, leaving those for downstream filters. The tradeoff is a non-flat passband response -- a sinc^N rolloff shape -- which typically requires a compensation FIR (a "droop correction" filter) in the stages that follow.
A CIC decimator of order N and decimation ratio R consists of N integrator stages running at the input rate, a downsampler, and then N comb stages running at the reduced output rate. The integrators accumulate without bound in theory, so register bit widths must be sized to prevent overflow: on an FPGA, each integrator stage requires up to N * log2(R) additional bits beyond the input width (ceiling to the next integer for practical register sizing, though the exact value depends on the fixed-point convention used). Getting this bit-growth calculation wrong is one of the most common implementation mistakes and leads to silent wrap-around distortion.
When implementing a CIC on an FPGA, the integrators running at high sample rates benefit from pipeline-friendly architectures. The comb sections, running at the lower output rate, are less timing-critical. On devices such as Xilinx 7-series or Intel (Altera) Cyclone/Arria families, a modest-order CIC (N=3 to 5) with decimation ratios up to a few hundred fits easily in fabric logic with no DSP blocks consumed. IP cores for CIC filters are available from most FPGA vendors, but hand-coded HDL or HLS implementations give tighter control over bit widths and latency.
For audio applications -- such as interfacing a PDM MEMS microphone, as explored in HDL audio interface tutorials -- a CIC decimator is often the first processing stage after the PDM bitstream enters the FPGA, bringing a 3 MHz or higher clock-rate bitstream down to a manageable audio sample rate (e.g., 48 kHz) before a compensation FIR polishes the frequency response.
Frequently asked
Why does a CIC filter need no multipliers?
The filter's coefficients are all unity. Each stage consists only of an accumulator (integrator: y[n] = y[n-1] + x[n]) and a differencer (comb: y[n] = x[n] - x[n-M]). Both operations map directly to adders and subtractors in hardware.
How do I calculate the required register width to prevent overflow in a CIC decimator?
For an N-stage CIC with decimation ratio R and input word width B_in, each integrator can grow by up to log2(R) bits per stage. The maximum internal bit width needed is B_in + N*ceil(log2(R)) bits. In practice, on an
FPGA you size all internal registers to this width and let the logic synthesizer trim unused bits. Truncating too early causes wrap-around distortion that is hard to detect in
simulation if test vectors don't exercise full-scale inputs.
What is the passband droop problem, and how is it fixed?
A CIC filter has a frequency response with a sinc^N rolloff shape (proportional to (sin(pi*f*R/fs) / (R*sin(pi*f/fs)))^N in the normalized form), which rolls off toward the edge of the passband even before the stopband. For audio or communications use the droop is corrected by following the CIC with a short compensation FIR whose response approximates the inverse sinc shape over the passband. This FIR operates at the decimated (low) rate, so it is inexpensive to implement.
When should I use a CIC filter instead of a polyphase FIR decimator?
CIC filters are the better choice when the decimation ratio is large (roughly 8 or higher) and the input data rate is high enough that running a full FIR at that rate would be prohibitively expensive in multipliers or DSP blocks. Polyphase FIR decimators offer more precise control over stopband attenuation and passband flatness but require multipliers at each tap. A common design pattern combines both: a CIC handles the bulk of the decimation, and a polyphase FIR handles a final factor of 2 to 4 while also correcting the CIC droop.
Can a CIC filter be used for interpolation as well as decimation?
Yes. A CIC interpolator reverses the stage order: comb sections run at the low input rate, an upsampler inserts zeros, and integrator sections run at the high output rate. The same bit-growth rules apply, and the sinc-shaped frequency response means a compensation FIR before the CIC is typically needed to pre-emphasize the signal and correct for the interpolation droop.
Differentiators vs similar concepts
A CIC filter is sometimes confused with a simple boxcar (moving average)
FIR filter. In the decimating CIC case, a single-stage CIC (N=1) is equivalent to a rectangular-window moving average of length R, but this equivalence depends on the specific CIC configuration and does not hold universally for every CIC variant. A multi-stage CIC (N>1) applies that averaging N times in cascade, producing a higher-order sinc^N response with much greater stopband attenuation. CIC filters are also distinct from polyphase FIR decimators: CICs require no multipliers and handle very large decimation ratios efficiently but have a fixed sinc-shaped response, while polyphase FIRs use multipliers to achieve an arbitrary, precisely specified frequency response.
