A Configurable Logic Block (CLB) is the fundamental repeating logic cell in Xilinx FPGAs, consisting of lookup tables (LUTs), flip-flops, carry-chain logic, and multiplexers that can be configured to implement arbitrary combinational and sequential logic. The CLB is the primary building block from which larger logic functions, state machines, and datapaths are constructed on Xilinx devices.
In practice
In Xilinx FPGAs, the CLB is organized into smaller units called slices. On Spartan-6 and many earlier devices, each CLB contains two slices; on 7-series and later devices (Artix-7, Kintex-7, Zynq, UltraScale), each CLB also contains two slices, though CLB organization varies by family and should be confirmed in the device architecture guide. Slices come in variants (SLICEL and SLICEM) with differing capabilities. Each slice in common 7-series and UltraScale families contains four 6-input LUTs and eight flip-flops, though the exact partitioning of resources can differ by family and configuration mode, giving the CLB count a direct relationship to a device's overall logic capacity. FPGA datasheets and synthesis tool reports express resource utilization in terms of LUTs and flip-flops within these slices, so understanding the CLB structure helps interpret what "85% utilization" actually means.
On SLICEM slices in Xilinx 7-series and UltraScale devices, LUTs can be configured not just as logic functions but also as small distributed RAM or shift registers (SRLs). This flexibility is a key optimization opportunity: a synthesis tool or a designer writing explicit HDL can exploit distributed RAM for small FIFOs or delay lines without consuming dedicated block RAM. The blog post "Inside the Spartan-6: Using LUTs to optimize circuits" covers practical examples of this kind of resource substitution.
Carry-chain logic within the CLB is critical for arithmetic performance. Ripple-carry adders implemented using the dedicated carry chain run significantly faster than adders built from general LUT fabric, because the carry propagates through a dedicated routing path rather than general interconnect. Synthesis tools target this automatically for addition and subtraction, but the carry chain is directional and constrained in how it can fan out, which occasionally creates placement challenges at high utilization.
Resource planning based on CLB count is part of device selection. Targeting a Spartan-3E XC3S500E (500K system gates, roughly 4,656 slices) versus a Spartan-6 XC6SLX45 (43,661 LUTs across 6,822 slices) involves understanding not just raw LUT count but also the ratio of available block RAM, DSP slices, and I/O to CLB fabric, since a design that is LUT-constrained may fit on a larger CLB device while still running out of block RAM or I/O on a smaller one.
Frequently asked
What is the difference between a CLB and a slice?
A
slice is the sub-unit inside a CLB. On Xilinx 7-series devices, each CLB contains two slices, and each slice contains four 6-input
LUTs and eight
flip-flops.
Synthesis reports and resource utilization figures typically cite LUTs and flip-flops directly rather than CLB counts, but the CLB is the physical tile that the place-and-route tool works with on the device floor plan.
What is the difference between SLICEL and SLICEM?
On Xilinx 7-series and UltraScale devices, SLICEM (memory-capable)
slices allow their
LUTs to be configured as
distributed RAM or SRL (shift register LUT) elements in addition to ordinary logic. SLICEL slices support
combinational logic, registered logic, carry logic, and other standard slice functions, but do not support distributed RAM or SRL modes. Roughly half the slices in most 7-series devices are SLICEM. If a design relies heavily on distributed RAM, the placer may become congested in regions with insufficient SLICEM slices.
How does CLB count relate to the 'system gate' or 'logic cell' figures in Xilinx datasheets?
Xilinx historically quoted 'system gates' as a marketing metric whose exact composition varied by era and product line, generally folding in contributions from CLB logic alongside other resources, making direct comparisons difficult. More reliable for planning purposes are the raw
LUT and
flip-flop counts per device, found in the device selection guide. For example, the Spartan-6 XC6SLX9 provides 5,720 LUTs; the XC6SLX150 provides 147,443 LUTs.
Synthesis tool reports after implementation give actual consumed LUT and FF counts.
Do other FPGA vendors use the term CLB?
CLB is Xilinx-specific terminology. Intel/Altera uses 'Logic Element' (LE) in Cyclone/MAX families and 'Adaptive Logic Module' (ALM) in Stratix/Arria/Cyclone V and later families. Lattice uses 'Logic Cell' or 'PFU' (Programmable Function Unit) depending on the family. The underlying concept of a repeating logic tile is common across vendors, but the internal organization, resource types, and naming differ significantly between architectures.
Can CLB flip-flops be used independently of the LUTs in the same slice?
Yes. The
flip-flops in a
slice can be driven by
LUT outputs or directly from slice inputs, so they are usable independently. This matters when a design is flip-flop-constrained rather than LUT-constrained: a high-speed pipeline with registered data paths may consume many FFs while leaving LUTs relatively free. Place-and-route tools handle this automatically, but awareness of the LUT-to-FF ratio in a target device helps during architecture planning.
Differentiators vs similar concepts
CLB is sometimes used loosely to mean any
FPGA logic cell, but it is specifically Xilinx terminology. Intel/Altera equivalents are the Logic Element (LE) in older families and the Adaptive Logic Module (ALM) in Stratix/Arria/Cyclone V and newer families. ALMs use a fracturable 8-input
LUT structure that differs architecturally from the Xilinx 6-input LUT in a CLB
slice. CLB also should not be confused with
block RAM (BRAM) or DSP slices, which are distinct hard resources placed alongside CLB fabric on the FPGA die and are not counted as part of CLB utilization.
