A clock enable (CE) is a synchronous control signal that gates the operation of a register, counter, or block of logic without gating the clock line itself: the clock continues to toggle, but the element only captures new data or advances state when CE is asserted.
In practice
In FPGAs, most flip-flop primitives expose a dedicated CE pin, though naming and implementation details vary by device family and register type. When CE is deasserted, the flip-flop ignores its D input and holds its current value. Because the clock net keeps running, clock-tree skew is unaffected and timing closure is simplified compared to gating the clock signal at the source, though the CE path itself still carries setup and hold requirements that must be met. Tools such as Xilinx ISE/Vivado and Intel Quartus generally map CE logic directly onto the flip-flop's CE pin, often consuming no additional LUT resources, though extra logic may be introduced in some cases such as polarity handling, fanout buffering, or complex enable conditions.
Clock enables are also the preferred mechanism for building multi-rate designs on a single clock domain. A counter that produces a one-cycle-wide pulse every N cycles can drive the CE input of downstream registers, effectively creating a divided rate without introducing a second clock domain or metastability hazards. This pattern appears in UART baud-rate generators, PWM timers, and display controllers. The blog post "VGA Output in 7 Slices. Really." demonstrates how aggressive use of CE-driven logic can minimize slice count in a single-clock design.
In ASIC and standard-cell design, the analogous construct is an integrated clock gating cell (ICG), which combines a latch and an AND gate in a glitch-free topology. The principle is the same: hold the enable signal stable during the active clock edge so the gated clock (or CE input) transitions only when safe. Power savings come from reducing the switching activity of registers downstream of the gate.
A common pitfall is driving CE from combinational logic that has glitches or excessive delay. Even though CE is synchronous on FPGA flip-flops, a CE signal that arrives late relative to the flip-flop's setup requirement will cause a timing violation; the CE path must meet its own timing constraints and should be treated with the same care as other critical control paths. Always constrain CE paths in your timing constraints file.
Frequently asked
Why use a clock enable instead of simply gating the clock signal?
Gating a clock signal introduces the risk of glitches that corrupt register state and makes it harder for the place-and-route tool to meet timing across the clock tree. A synchronous CE keeps a single, clean clock network running everywhere and lets the
flip-flop's dedicated CE pin control whether new data is loaded on each clock edge, which is both safer and easier to analyze statically.
Does asserting CE consume extra power compared to just letting the flip-flop toggle?
Holding CE deasserted reduces power because the
flip-flop's internal nodes stop switching, lowering dynamic power. This is the same principle behind
FPGA power-gating strategies and
ASIC clock gating: every toggle that does not happen saves a small amount of CV²f energy. The savings become meaningful when large register banks or block RAMs are idle for long periods.
How does a CE-based rate divider work?
A free-running counter, clocked at the system rate, asserts its terminal-count output for exactly one cycle when it wraps. That pulse feeds the CE pin of downstream registers. Those registers then update at 1/N of the system clock rate while remaining in the same clock domain, so no
metastability analysis is needed. This technique is covered in the context of clock and counter construction in 'Designing a
FPGA Micro Pt1 - Start The Clock' and 'Designing a FPGA Micro Pt2 - Clock and Counter build and test.'
On an FPGA, what happens to the CE signal if I do not connect the CE pin of a primitive?
Most
FPGA synthesis tools tie the CE pin high by default if it is left unconnected, meaning the
flip-flop updates every cycle. If you infer registers in
HDL without an explicit enable, the synthesizer will typically do the same. Leaving CE permanently high wastes the capability but is functionally equivalent to a standard D flip-flop.
Is clock enable the same concept as a write enable on a memory?
They are closely related but not identical. A write enable on a synchronous RAM also qualifies the clock edge for the memory array, so functionally it plays the same role as CE. Some memory primitives, such as Xilinx block RAMs, expose both a clock enable for the port registers and a separate write enable for the memory array, and the two can be controlled independently.
Differentiators vs similar concepts
Clock enable (CE) is sometimes confused with clock gating. Clock gating physically stops the clock signal from reaching a register or block, typically via an AND or OR gate on the clock net. CE leaves the clock running and instead tells the
flip-flop to ignore its input; the distinction matters for timing closure,
glitch risk, and tool support. On FPGAs, true clock gating is generally discouraged because it disrupts the dedicated clock network; CE on flip-flop primitives is the recommended alternative. In
ASIC flows, integrated clock gating cells (ICGs) are standard for power reduction and are a proper gating construct, not a CE, though the architectural intent is similar.
