Combinational logic is digital logic in which the output at any moment depends only on the current inputs, with no internal state or memory elements. The same input combination always produces the same output, regardless of past inputs or the order in which inputs changed.
In practice
In embedded systems, combinational logic appears wherever a result can be derived purely from present inputs: address decoders, multiplexers, parity generators, ALU datapaths, priority encoders, and glue logic between peripherals. On discrete-gate boards it is built from AND/OR/NAND/NOR/XOR gates; in FPGAs, it is most commonly synthesized into look-up tables (LUTs). The blog post "Inside the Spartan-6: Using LUTs to optimize circuits" covers how Xilinx FPGAs implement combinational functions inside their configurable logic blocks.
A key practical concern is propagation delay. Every gate introduces a small delay, and long chains of gates -- called the critical path -- limit how fast the design can be clocked. In MCU glue logic and FPGA designs alike, tools report worst-case path delays so designers can identify and shorten bottlenecks. The blog post "One Clock Cycle Polynomial Math" illustrates how a carefully arranged combinational datapath can complete a non-trivial computation within a single clock cycle.
Combinational logic is the building block of more complex structures. Sequential logic adds flip-flops or latches, which store state between clock edges. State machines pair combinational next-state and output logic with a register holding the current state. The blog posts "Use a Simple Microprogram Controller (MPC) to Speed Development of Complex Microprogrammed State Machines" and "Use Microprogramming to Save Resources and Increase Functionality" show how combinational decode logic plays a central role in microprogrammed controllers.
A common pitfall is unintended latches. In HDL (VHDL or Verilog), if a combinational always/process block fails to assign an output for every possible input combination, synthesis tools typically infer a latch to hold the last value. Latches are not the same as flip-flops and often cause timing analysis problems. Fully specifying all output assignments -- or using a default assignment at the top of the block -- prevents this.
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Discussed on FPGARelated
Frequently asked
What is the difference between combinational logic and sequential logic?
Combinational logic has no memory: outputs depend only on current inputs. Sequential logic includes storage elements (
flip-flops or latches) so that outputs also depend on past inputs captured as stored state. In practice, most digital systems mix both: combinational logic computes new values, and registers sample those values on a clock edge.
How is combinational logic implemented in an FPGA?
Most
FPGA families implement combinational functions using look-up tables (
LUTs). A LUT is essentially a small SRAM whose address lines are the logic inputs and whose stored contents define the desired truth table. A 6-input LUT can implement any Boolean function of up to six variables. The
synthesis tool maps your
HDL expressions onto LUTs automatically, optimizing for speed or area.
Why does combinational logic have a maximum speed limit?
Each gate introduces a propagation delay, typically measured in nanoseconds or picoseconds. When inputs change, the effect ripples through the chain of gates before the output settles to its correct value. The longest such chain -- the critical path -- determines the minimum time that must elapse before the output is valid. In a clocked design, the clock period must be longer than this worst-case delay plus setup-and-hold margins of the destination
flip-flop.
What is a glitch (hazard) in combinational logic, and does it matter in embedded designs?
A
glitch (also called a hazard) is a brief spurious output transition that occurs while inputs are changing and different signal paths through the logic settle at different rates. In purely combinational paths feeding
flip-flops, glitches generally do not matter because the flip-flop only samples at the clock edge, long after the output has settled. Glitches become a problem when the combinational output drives an asynchronous input such as a
clock enable, an interrupt line, or an asynchronous reset, where even a short pulse can cause unintended state changes.
How do I avoid accidentally inferring latches when writing combinational logic in HDL?
In
Verilog, assign every output of a combinational always block under all branches of every if/case statement. In
VHDL, cover all conditions in the process and assign every signal in every branch. A common idiom is to assign default values to all outputs at the very start of the block, then override them in specific branches. Most
synthesis tools will warn when a
latch is inferred; treat these warnings as errors until you have confirmed the latch is intentional.
Differentiators vs similar concepts
Combinational logic is often contrasted with sequential logic. The distinction is memory: combinational circuits have none, so the output is a pure function of present inputs; sequential circuits contain
flip-flops or latches that retain state across time. The two are frequently confused when describing
HDL code blocks -- an always/process block intended to be combinational will silently become sequential if the
synthesis tool infers a
latch due to incomplete output assignment. The term "combinatorial" is an alternate spelling used interchangeably with "combinational" in the literature; there is no technical difference between them.
