A Complex Programmable Logic Device (CPLD) is a type of programmable logic chip that implements combinational and registered logic through an array of macrocells connected by a programmable interconnect. CPLDs are typically used when predictable, fast pin-to-pin timing and non-volatile configuration storage matter more than the large gate counts offered by FPGAs.
In practice
CPLDs appear most often as glue logic between other chips, replacing banks of discrete 74-series logic gates with a single reprogrammable device. Typical jobs include address decoding, bus bridging, signal conditioning, level shifting control, and generating chip-select signals with deterministic timing. Because most CPLDs store their configuration in on-chip flash or EEPROM, they are ready immediately at power-on without an external configuration bitstream, unlike most SRAM-based FPGAs. (Some CPLD families and a small number of nonvolatile FPGA families also power up without an external source, so this distinction is a practical generalization rather than a universal rule.)
Timing in a CPLD is generally more predictable than in most FPGAs: datasheets for many families specify a worst-case pin-to-pin propagation delay (for example, 5–10 ns on devices like the Xilinx XC9500XL or Lattice ispMACH 4000 series). The actual delay still depends on the specific device family, routing path, speed grade, temperature, and output loading, but this figure gives designers a concrete upper bound that FPGA place-and-route variability can make harder to guarantee. This makes CPLDs attractive in timing-critical glue paths where that variability would complicate sign-off.
CPLDs are architecturally built around product-term logic: each macrocell can sum a configurable number of AND-plane product terms, feeding a flip-flop or combinational output. This suits wide, shallow logic functions well, but deep pipelined or memory-heavy designs are better handled by an FPGA. Gate counts on CPLDs are modest — typically ranging from a few hundred to around 10,000 equivalent gates on mainstream parts, though equivalent-gate figures are an approximate metric and some families fall outside this range.
For embedded developers new to programmable logic, CPLDs are often a gentler entry point than FPGAs. The design flow -- writing VHDL or Verilog, synthesizing, fitting, and programming via JTAG -- is the same toolchain discipline used for FPGAs, making CPLDs a practical learning step. The blog post "My VHDL <= monpjc; Journey" illustrates this kind of progression through programmable logic design.
Frequently asked
What is the main architectural difference between a CPLD and an FPGA?
CPLDs use a sum-of-products macrocell architecture with a centralized programmable interconnect, providing predictable timing and immediate power-on readiness via non-volatile on-chip storage in most families. FPGAs use a fine-grained
LUT-based fabric with dedicated
block RAM, DSP
slices, and often high-speed transceivers, enabling much higher densities and complex designs, but most SRAM-based FPGAs require an external configuration source and have timing that depends heavily on place-and-route results. For a closer look at the
FPGA LUT fabric, the post 'Inside the Spartan-6: Using LUTs to optimize circuits' covers that side of the divide.
Do CPLDs need an external flash chip to store their configuration at power-off?
For most mainstream CPLDs, no — this is one of their defining practical advantages. Parts like the Xilinx XC9500XL, Lattice ispMACH 4000ZE, and Altera (Intel) MAX series store configuration in on-chip flash or EEPROM, so the device is fully programmed and operational immediately at power-on. Most SRAM-based FPGAs, by contrast, lose their configuration when power is removed and must load a
bitstream from an external
SPI flash or other source during boot. Note that not every CPLD family uses on-chip nonvolatile storage, so it is worth confirming the configuration architecture for the specific part you select.
How are CPLDs programmed, and can they be reprogrammed in-system?
Most modern CPLDs are programmed over
JTAG (IEEE 1149.1), and many support in-system programming (ISP), meaning the device can be reprogrammed while soldered to the board without removing it. ISP support is vendor- and family-dependent, so confirm it in the datasheet for your specific part. The vendor toolchain (
Xilinx ISE/
Vivado, Lattice Diamond/iCEcube, Intel Quartus) generates a JEDEC or
SVF file that a JTAG programmer downloads to the device. Reprogramming endurance is finite -- typically rated at 1,000 to 10,000 erase/program cycles depending on the part.
When should I choose a CPLD over a small FPGA?
Choose a CPLD when you need guaranteed power-on readiness without a boot loader, a fixed worst-case pin-to-pin propagation delay from the datasheet, low static power (several CPLD families are designed for low standby current), or a BOM that avoids an external configuration flash. Choose a small
FPGA when your logic depth, gate count, or need for
block RAM and DSP resources exceeds what a CPLD macrocell architecture can efficiently fit, or when you need IP cores that assume an FPGA fabric.
Can a CPLD implement a simple CPU or state machine?
Yes, CPLDs can implement small finite state machines and even minimal CPU-like controllers, though their modest gate counts and lack of
block RAM limit complexity. A CPLD is well suited to a controller with a handful of states and registered outputs. Implementing a more capable CPU with registers, an ALU, and instruction memory would quickly exhaust even a larger CPLD and is generally better targeted at an
FPGA; the post 'PC and SP for a small CPU' touches on the register structures involved in that kind of design.
Differentiators vs similar concepts
CPLDs are most often confused with FPGAs. Both are reprogrammable logic devices programmed in
HDL (
VHDL or
Verilog), but they differ in architecture, capacity, and configuration. CPLDs use a product-term macrocell fabric with a centralized interconnect and non-volatile on-chip storage in most families, resulting in predictable pin-to-pin timing, instant power-on operation, and modest gate counts (typically up to ~10K equivalent gates, though this metric is approximate and some families fall outside that range). FPGAs use a fine-grained
LUT fabric often paired with
block RAM, DSP blocks, and high-speed I/O, supporting far higher complexity, but most SRAM-based FPGAs require an external configuration source at every power-up and have timing that varies with placement and routing; some nonvolatile
FPGA families are exceptions to this. CPLDs are also sometimes confused with PALs and GALs, which are their simpler predecessors: PAL/GAL architectures generally offer a single programmable AND plane feeding fixed or limited output logic with far fewer macrocells than a CPLD, while a CPLD integrates multiple PAL-like blocks with a programmable interconnect between them. The exact structure varies across PAL/GAL families, but all are significantly less flexible than even a modest CPLD.
