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DLL

Category: Io-and-clocking | Also known as: Delay-Locked Loop

A Delay-Locked Loop (DLL) is a closed-loop clock-conditioning circuit that uses a chain of delay elements and a feedback comparator to align an output clock edge to an input reference edge, eliminating or compensating for clock distribution skew. Unlike a Phase-Locked Loop (PLL), a DLL does not use a voltage-controlled oscillator; it delays the reference signal rather than synthesizing a new frequency, though some DLL-labeled FPGA primitives include auxiliary logic that extends this basic capability.

In practice

DLLs appear most often in FPGAs and high-speed memory interfaces. In FPGAs such as the Xilinx Spartan/Virtex families and Intel (Altera) Cyclone/Arria series, on-chip DLL primitives (sometimes called DCMs on older Xilinx devices) are used to deskew the global clock tree, generate phase-shifted versions of a clock, or produce a clean, edge-aligned clock for I/O capture. DDR SDRAM controllers and discrete memory chips commonly use DLLs or similar delay-based circuits to align the data strobe (DQS) signal within the data eye, allowing reliable sampling at high data rates, though the specific approach on the controller side may involve a DLL, PLL, or other delay elements depending on the platform.

In practice, a DLL works by measuring the phase difference between the reference input and the delayed output, then adjusting tap selection in the delay line until the error is driven to zero. Because it delays rather than multiplies, a pure DLL cannot perform frequency synthesis on its own. However, it can produce simple rational multiples of the input frequency (e.g., half-rate or double-rate clocks) on some implementations through additional circuitry, and it typically achieves lock faster than a PLL.

A key pitfall is the limited operating frequency range: each delay-line tap has a fixed minimum and maximum delay set by process, voltage, and temperature (PVT). If the input clock period falls outside the range the delay line can cover end-to-end, the DLL cannot lock. On FPGAs, this is expressed as a minimum/maximum input frequency specification for each DLL/DCM primitive, and violating it will typically result in a failure to lock, though the exact failure behavior can vary by device family and implementation. Designers must verify timing across PVT corners and consult the device datasheet for lock-time and jitter specifications.

Jitter behavior differs from a PLL. Because a DLL directly tracks the input reference on every cycle, it has limited ability to average out cycle-to-cycle jitter; input jitter tends to pass through with less attenuation than in a PLL, though the degree of attenuation depends on loop bandwidth and implementation details. For applications requiring jitter filtering, a PLL is often the better choice, though this is a practical guideline rather than a strict rule, as PLL noise characteristics also depend on configuration. For applications requiring low latency, deterministic phase alignment, and fast lock, a DLL is often preferred.

Frequently asked

What is the fundamental difference between a DLL and a PLL?
A PLL uses a voltage-controlled oscillator (VCO) in its feedback path, allowing it to synthesize new frequencies and filter jitter. A DLL uses a variable delay line instead; it can only delay the input clock, not generate an independent frequency. This means a DLL cannot multiply or divide frequency on its own (without auxiliary logic), but it locks faster and introduces less phase noise from an oscillator.
Why do FPGA datasheets list a minimum input frequency for DLL/DCM primitives?
The delay line in a DLL has a maximum total delay bounded by the sum of all its taps. If the input clock period is longer than that maximum delay, the feedback comparator cannot find a lock point, and the DLL fails to lock. The minimum frequency specification is therefore determined by the maximum delay the line can introduce, which varies with silicon process, supply voltage, and temperature.
Can a DLL be used for clock frequency multiplication?
A pure DLL cannot multiply frequency because it has no oscillator. Some FPGA primitives labeled as DLLs (for example, older Xilinx DCMs) include additional logic or use the delay line in a ring configuration to achieve integer frequency multiplication, but that functionality goes beyond a textbook DLL. Check the specific device documentation to see what operations a given primitive supports.
How does a DLL help in DDR memory interfaces?
DDR SDRAM uses a data strobe (DQS) that is edge-aligned with data at the DRAM output. By the time DQS reaches the controller, it has accumulated board and package delay. A DLL in the controller (or inside the DRAM itself) shifts the strobe by 90 degrees or adjusts it to be center-aligned within the data eye, giving the capture flip-flop maximum setup and hold margin.
Does input clock jitter affect a DLL output more than it affects a PLL output?
Generally yes. A PLL's VCO and loop filter act as a low-pass filter on the input phase, attenuating high-frequency (cycle-to-cycle) jitter. A DLL tracks the input edge on every cycle, so cycle-to-cycle jitter on the reference tends to appear on the output with less attenuation than in a PLL, though the exact jitter transfer depends on the DLL's loop bandwidth and implementation. For jitter-sensitive applications such as high-speed serial links, a PLL is typically preferred over a DLL.

Differentiators vs similar concepts

DLL vs. PLL: Both condition clocks and can produce phase-shifted outputs, but a PLL uses a VCO and can synthesize arbitrary (within limits) output frequencies while filtering input jitter. A DLL uses a delay line, cannot generate new frequencies independently, locks faster, and passes input jitter more directly to the output. In many FPGA families both primitives exist side by side; PLLs/MMCMs are used when frequency synthesis or jitter filtering is needed, while DLLs are used for low-latency phase alignment and I/O deskew.
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