Duty cycle is the ratio of the active (high) time of a periodic signal to its total period, expressed as a percentage. A signal with a 25% duty cycle is high for one quarter of each period and low for the remaining three quarters.
In practice
Duty cycle is most commonly encountered when configuring PWM peripherals. On most MCUs, a hardware timer generates PWM by comparing a running counter against two registers: one that sets the period and one that sets the compare value. The ratio of the compare value to the period register approximates the duty cycle in common configurations, though the exact relationship depends on the counting mode, polarity settings, and whether the timer uses inclusive or exclusive counting. On STM32 timers, for example, setting ARR to 999 and CCR to 499 gives a 50% duty cycle at whatever frequency the timer clock and prescaler define.
In power and motor control applications, duty cycle directly controls the average energy delivered to a load. A brushed DC motor driven at 75% duty cycle receives approximately 75% of the supply voltage on average, though actual current and torque depend on motor inductance, PWM frequency, and drive topology. Similarly, switching regulators rely on duty cycle to set the output voltage: for an ideal buck converter the steady-state relationship is Vout = D * Vin, while a boost converter follows a different relationship (Vout = Vin / (1 - D)).
Duty cycle resolution is a practical constraint often overlooked at the design stage. Resolution is primarily determined by the number of counter ticks per period, though factors such as center-aligned counting modes and dead-time insertion can affect effective resolution. A timer running at 72 MHz with a 10 kHz PWM frequency has 7200 ticks per period, giving about 13-bit resolution. Dropping to 100 kHz leaves only 720 ticks, reducing resolution to roughly 10 bits. The blog posts "MyHDL ... MyPWM" and "Yet another PWM" explore PWM generation in FPGAs, where the same trade-off between frequency and resolution appears.
A 0% duty cycle (output always low) and 100% duty cycle (output always high) are valid logical extremes but require care: some timer peripherals cannot actually reach these limits, and driving a switching converter at 0% or 100% for extended periods may be unsafe depending on the converter topology and control scheme. Always check the peripheral reference manual for minimum and maximum achievable duty cycle values.
Frequently asked
What is the difference between duty cycle and frequency?
Frequency describes how many complete cycles occur per second and is the reciprocal of the period. Duty cycle describes the fraction of each cycle during which the signal is active. The two are independent: you can have a 1 kHz signal at any duty cycle from 0% to 100%, and a 50% duty cycle signal at any chosen periodic frequency.
How do I calculate the duty cycle register value for a given percentage on a typical MCU timer?
As a rule of thumb, multiply the desired duty cycle fraction by the period register value. If the period register (ARR on STM32, PR on PIC) is set to N counts, a duty cycle of D% requires a compare register value of approximately (D / 100) * N. For example, 30% on a period of 1000 counts gives a compare value of 300. The exact formula may vary by MCU depending on whether the period register count is inclusive, whether the counter starts at 0 or 1, and the output polarity mode, so always verify against the peripheral reference manual.
Why does increasing PWM frequency reduce duty cycle resolution?
Resolution is set by the number of timer ticks in one period. Fewer ticks per period means fewer discrete steps between 0% and 100%. At a fixed timer clock of 48 MHz, a 1 kHz PWM has 48000 ticks (~15-bit resolution), while a 100 kHz PWM has only 480 ticks (~9-bit resolution). Choosing a higher timer clock or accepting a lower PWM frequency are the common remedies.
Can duty cycle be applied to signals other than PWM outputs?
Yes. Any periodic digital signal has a duty cycle, including clock signals, serial bus lines during sustained transmission, and sensor outputs like those from Hall-effect sensors or certain encoders that encode position as a duty cycle rather than a frequency. Quartz oscillators and clock buffers are often characterized by their output duty cycle, with 50% being ideal for circuits that trigger on both edges.
What is 'duty cycle distortion' and why does it matter?
Duty cycle distortion (DCD) is a deviation from the intended duty cycle caused by differences in rise and fall times, propagation delays, or voltage threshold asymmetries in a signal path. It matters in high-speed clock distribution and in applications like motor control where asymmetric drive times cause uneven torque or audible noise. On-chip clock management units often include duty-cycle correction circuitry to compensate.
Differentiators vs similar concepts
Duty cycle is sometimes conflated with pulse width. Pulse width is an absolute time (e.g., 500 microseconds), while duty cycle is a dimensionless ratio relative to the period. Changing the frequency while keeping the pulse width constant changes the duty cycle; changing the frequency while keeping the duty cycle constant changes the pulse width. Both terms appear in timer/PWM documentation, so it is worth confirming which quantity a given API or register controls.
