Xilinx EDK (Embedded Development Kit) was a suite of tools from Xilinx for designing, integrating, and debugging embedded processor systems on Xilinx FPGAs, targeting both the soft-core MicroBlaze processor and the hard-core PowerPC 405/440 blocks present in certain Virtex devices. It combined hardware platform specification, IP integration, and software development into a unified environment, and has since been superseded by Xilinx Vivado/Vitis (and previously PlanAhead/SDK).
In practice
EDK centered on two main tools: XPS (Xilinx Platform Studio) for hardware design and IP integration, and SDK (Software Development Kit) for writing, compiling, and debugging the embedded software. A designer would build a processor system in XPS by instantiating IP cores from a catalog, wiring peripherals to the processor bus (PLB or AXI), and exporting a hardware description to SDK, where application code was compiled against board-support packages (BSPs) auto-generated from that description.
The MicroBlaze soft-core processor was the most common EDK target on Spartan and Virtex FPGAs that lacked a hard CPU. Virtex-II Pro, Virtex-4, and Virtex-5 devices optionally used the hard PowerPC 405 or 440 core instead. EDK supported both paths with the same workflow, though BSP and linker script details differed between them.
A recurring workflow challenge was keeping the hardware and software projects synchronized. Regenerating the hardware in XPS and re-exporting the hardware handoff file was required whenever peripheral addresses, interrupt assignments, or bus widths changed; failing to re-export was a common source of mysterious software failures. Makefiles were an alternative to the GUI for scripting these steps, as covered in the blog post "Makefiles for Xilinx Tools."
Xilinx transitioned away from EDK in a staggered fashion beginning around 2013-2014, introducing Vivado IP Integrator plus Xilinx SDK for 7-series and later UltraScale devices while EDK/ISE remained the supported flow for older families. SDK was later replaced by the Vitis unified software platform in 2019. Legacy projects targeting older device families such as Spartan-6 or Virtex-6 may still require EDK, since those families are not supported in Vivado.
Discussed on FPGARelated
Frequently asked
What replaced Xilinx EDK?
For 7-series and newer Xilinx FPGAs, the hardware integration role of XPS moved to
Vivado IP Integrator, and the software development role of SDK was first replaced by standalone Xilinx SDK and then by Vitis (introduced in 2019). The transition was staggered across device families and tool releases rather than a single clean cutoff. Older device families such as Spartan-6 and Virtex-6 are not supported in Vivado, so EDK/
ISE remains the legacy toolchain for those parts, though the exact tool requirement depends on the specific device and supported tool versions.
What is MicroBlaze and how does it relate to EDK?
MicroBlaze is a 32-bit soft-core RISC processor implemented in
FPGA fabric. It is configurable at
synthesis time -- cache sizes, FPU inclusion, exception handling, and bus interfaces are all optional. EDK was the primary tool for instantiating and configuring MicroBlaze, connecting it to on-chip peripherals, and building the software that runs on it. MicroBlaze itself continues to be supported in the
Vivado/Vitis flow.
What is the hardware handoff file in EDK, and why does it matter?
The hardware handoff is an exported set of hardware description artifacts that XPS produces after hardware
synthesis and passes to SDK. The exact format and files involved vary by EDK version and flow, but the handoff conveys the memory map, peripheral base addresses, interrupt IDs, and processor configuration. SDK uses it to auto-generate BSPs and linker scripts. If the hardware changes and the handoff is not re-exported, the software build will target stale addresses and peripheral assumptions, causing hard-to-diagnose runtime failures.
What bus architectures were used in EDK designs?
Earlier EDK designs used the PLB (Processor Local Bus), a Xilinx/IBM bus common in PowerPC-based systems and early
MicroBlaze designs. Xilinx later adopted ARM's
AXI4 (part of the AMBA specification) as the dominant interconnect for MicroBlaze and Zynq designs, reflecting the industry shift toward AXI, though older or custom flows may use other interconnects. Many IP cores exist in both PLB and AXI variants; migrating between them required IP substitution in XPS rather than a simple setting change.
Can EDK be scripted or used without the GUI?
Yes. XPS exposed a Tcl-based command interface, and the underlying tools (xps, xpsbs, mb-gcc, etc.) are command-line programs. This made it practical to drive builds from Makefiles or shell scripts, which was useful for continuous integration and reproducible builds. The blog post 'Makefiles for Xilinx Tools' covers this approach in detail.
Differentiators vs similar concepts
EDK is sometimes conflated with
ISE (Xilinx ISE Design Suite), but ISE was the broader
RTL synthesis and implementation toolchain for all Xilinx
FPGA designs. EDK was a separate, embedded-focused layer built on top of ISE, specifically for processor-centric designs. SDK, the software IDE within EDK, is also sometimes referred to as if it were EDK itself; strictly, SDK was one component of EDK, not the whole suite. In the
Vivado era, "Xilinx SDK" became a standalone product, which adds to the naming confusion.
