A Finite Impulse Response (FIR) filter is a discrete-time linear filter whose output is computed as a weighted sum of a finite number of past and present input samples, with no feedback from past outputs. Because it has no recursive terms, an FIR filter is inherently stable and can be designed to have a perfectly linear phase response when its coefficients are symmetric or anti-symmetric.
In practice
FIR filters appear throughout embedded DSP work wherever signal conditioning is needed: anti-aliasing before an ADC, reconstruction after a DAC, channel equalization in communications, decimation and interpolation in sample-rate conversion, and DC removal. The core operation is a multiply-accumulate (MAC) loop over N coefficients (the filter "taps"), where N directly controls frequency selectivity -- sharper roll-off requires more taps. On a microcontroller, a 64-tap FIR at 48 kHz can typically be handled by a Cortex-M4F using the CMSIS-DSP `arm_fir_f32` or fixed-point `arm_fir_q15` functions, though actual headroom depends on clock speed, memory placement, and interrupt load. On a PIC or AVR without a hardware multiplier, the same filter may consume a significant portion of the CPU budget, depending on the specific device and clock configuration.
FPGAs are a common deployment target for FIR filters when high sample rates, many parallel channels, or very low latency are required -- cases where a software loop cannot keep up. In an FPGA, the MAC chain is typically pipelined across fabric or mapped into dedicated DSP slices (e.g., Xilinx DSP48E2, Intel/Altera DSP blocks). Symmetric coefficient sets, which arise naturally from linear-phase FIR design, allow the "add-before-multiply" optimization that cuts the DSP slice count roughly in half. The blog post "FPGA or DSP Processor - Parameters to Make the Right Choice" discusses the trade-offs between these two implementation paths in more detail.
Fixed-point coefficient quantization is the most common pitfall in FIR implementation. Coefficients computed in floating-point must be scaled and rounded to fit a fixed-point word (commonly Q15 or Q31 on MCUs, or a custom width on FPGAs). Quantization can alter passband ripple, stopband attenuation, cutoff placement, and phase relative to the original floating-point design. The blog post "Dealing With Fixed Point Fractions" covers the practical mechanics of this scaling step. Always verify the quantized filter response with a frequency sweep or Fourier analysis of the impulse response before committing to hardware.
Tap count and coefficient symmetry also affect memory and timing. Each tap requires one coefficient stored in memory and one MAC operation per output sample. For a real-time system, ensure the total MAC count fits within one sample period. On FPGAs, resource-sharing architectures (using a single multiplier time-multiplexed across taps) trade throughput for area, while fully parallel architectures maximize throughput at the cost of DSP slice count. For very high-rate designs, polyphase decomposition can distribute the computation across multiple lower-rate filter branches.
Discussed on FPGARelated
Frequently asked
What is the difference between an FIR and an IIR filter?
An FIR filter computes its output from a finite window of input samples only, with no feedback path. An IIR (Infinite Impulse Response) filter feeds previous output samples back into the computation, which can achieve a desired frequency response with fewer coefficients but introduces potential instability and non-linear phase. FIR filters are preferred when linear phase is required (e.g., data communications, audio) or when unconditional stability is a hard constraint. IIR filters are preferred when coefficient count or computation cost must be minimized and phase distortion is acceptable.
How do I choose the number of taps?
Tap count is primarily determined by the transition bandwidth -- the frequency range between the passband edge and the stopband edge. Narrower transitions require more taps. A rough rule of thumb for a Parks-McClellan or windowed-sinc design is N ≈ (stopband_attenuation_dB × sample_rate) / (22 × transition_bandwidth), though exact numbers depend on the design method and ripple spec. Double the tap count estimate and verify the quantized response before finalizing.
Why does a linear-phase FIR introduce a constant time delay?
A linear-phase FIR with N taps has a group delay of (N-1)/2 samples, which is constant across all frequencies. This means all frequency components are delayed by the same amount, preserving waveshape. For an N=65 tap filter at 48 kHz, the group delay is 32 samples, or about 667 microseconds. This delay is deterministic and can be compensated for in systems where absolute latency matters, but it cannot be eliminated without moving to a non-linear-phase design or an IIR filter.
How are FIR filters implemented efficiently on an FPGA?
On an
FPGA, FIR filters are most commonly mapped onto dedicated DSP
slices (such as Xilinx DSP48E2 or Intel DSP blocks) arranged in a pipelined MAC chain. For symmetric-coefficient (linear-phase) designs, the pre-addition trick -- summing the input sample and its mirror before the multiply -- halves the number of multiplications and thus the
DSP slice count. Tools like Xilinx FIR Compiler or Intel DSP Builder can generate optimized
RTL automatically. The blog post 'Developing FPGA-DSP IP with Python' discusses a Python-based workflow for generating and verifying such IP. For very high-rate designs, polyphase decomposition distributes computation across multiple parallel filter paths.
Can I use floating-point coefficients directly in an embedded FIR implementation?
On MCUs with an FPU (e.g., Cortex-M4F, Cortex-M7),
floating-point FIR implementations are practical and CMSIS-DSP provides `arm_fir_f32` for this purpose. On MCUs without an FPU, software floating-point is substantially slower than fixed-point -- often by a large factor depending on the core, compiler, and algorithm -- and is usually too expensive for real-time use. On FPGAs, floating-point datapaths consume significantly more DSP
slices and routing than fixed-point equivalents and are used mainly when dynamic range requirements cannot be met by fixed-point. Fixed-point Q15 or Q31 representations are the norm for most embedded FIR deployments.
Differentiators vs similar concepts
FIR vs. IIR: An IIR filter uses feedback (recursive) terms, achieving a given frequency selectivity with fewer coefficients than an FIR, but at the cost of potential instability and non-linear phase. FIR filters are always stable (no poles outside the unit circle) and can achieve exact linear phase by using symmetric coefficients; IIR filters cannot. FIR vs. moving average: A moving average is a special case of an FIR filter where all N coefficients are equal (1/N), giving a simple lowpass response with poor stopband attenuation. A general FIR filter uses optimized, unequal coefficients to meet a specified frequency mask.
