A flip-flop (FF) is a bistable sequential logic element that stores one bit of state, holding its output stable until a triggering event, most commonly a clock edge, causes it to sample and latch a new value. Flip-flops are the fundamental building block of registers, state machines, and pipelines, and are the standard storage element in synchronous digital logic.
In practice
In FPGA and CPLD designs, every register bit maps directly to a flip-flop in the device fabric (duplication for timing optimization is possible but not the normal case). Synthesis tools infer FFs from RTL constructs such as clocked `always` blocks in Verilog or clocked processes in VHDL. The number of available FFs is a primary resource metric reported after place-and-route and directly constrains how many bits of state a design can hold. On devices like the Xilinx 7-series or Intel Cyclone families, each logic element or slice contains a fixed ratio of LUTs to FFs, so designs that are FF-limited may have LUT headroom left over, or vice versa.
In microcontroller and ASIC contexts, flip-flops appear inside peripheral registers, pipeline stages, and bus interfaces, but embedded developers typically interact with them indirectly through C register writes rather than structural instantiation. The D-type edge-triggered FF is by far the most common variety in synchronous logic. SR, JK, and T types also exist and are encountered in older discrete logic, textbooks, and occasionally in specialized FPGA primitives, but are rarely instantiated explicitly in modern RTL.
A key practical concern is setup and hold time: the input data must be stable for a minimum setup time before the active clock edge, and must remain stable for a minimum hold time after it. Violating either constraint produces metastability, where the FF output can take an unpredictably long time to resolve to a valid logic level. This is a real failure mode when crossing clock domains, and is handled with synchronizer chains (typically two or more cascaded FFs clocked by the destination clock).
For embedded developers working with soft-core CPUs or custom state machines on FPGAs, FF count becomes a concrete design constraint. Blog posts such as "Use a Simple Microprogram Controller (MPC) to Speed Development of Complex Microprogrammed State Machines" and "Use Microprogramming to Save Resources and Increase Functionality" illustrate how microprogrammed approaches can reduce the state register width and FF usage compared to fully-encoded one-hot or binary state machines.
Learn this in FPGA Fundamentals
Frequently asked
What is the difference between a latch and a flip-flop?
A
latch is level-sensitive: its output follows the input while the enable signal is asserted, and holds when the enable is deasserted. A flip-flop is edge-triggered: it samples the input only on a specific clock edge (rising or falling) and does not respond to input changes between clock edges under normal operating conditions (asynchronous set/reset pins, if present, are an exception). In synchronous
FPGA and
ASIC design, latches are generally avoided because they complicate static timing analysis and can cause
glitch-induced state corruption.
Synthesis tools will warn when
RTL inadvertently infers a latch, which often indicates an incomplete if/case statement.
What is metastability, and why does it matter in embedded systems?
Metastability occurs when a flip-flop's setup or hold time is violated, leaving its output in an indeterminate state. Resolution time is not fixed, but the probability of remaining unresolved decays exponentially with time, so in practice the output usually settles quickly -- however, it can occasionally take long enough to cause downstream logic errors. In embedded systems this commonly happens when an asynchronous signal (a button press, an external interrupt, or data crossing from one clock domain to another) is sampled by a FF clocked at an unrelated frequency. The standard mitigation is a synchronizer: two or more FFs in series clocked by the destination clock. The probability of a metastability event propagating through both stages is exponentially lower, though never exactly zero. MTBF calculations for synchronizers are a standard part of high-reliability design.
How does FF count affect FPGA resource utilization?
FPGA place-and-route tools report FF usage as a percentage of available flip-flops in the device. Each storage bit in a design consumes at least one FF. Wide data paths, deep pipelines, and large state machines all increase FF demand. On Xilinx 7-series devices, each
slice contains 8 FFs (organized as two groups of 4, each associated with a set of
LUTs); on Intel (Altera) Cyclone IV devices, each logic element contains 1 FF, though multiple logic elements are grouped into a logic array block (LAB). If FF utilization is high, options include reducing pipeline depth, sharing state registers, encoding state machines more compactly, or moving to a larger device.
What flip-flop types are commonly available in FPGAs?
Most
FPGA families expose the D-type edge-triggered FF as the native primitive, often with synchronous or asynchronous set/reset and clock-enable inputs. JK, T, and SR types are not typically available as dedicated primitives but can be built from D-FFs plus
combinational logic.
Synthesis tools will automatically implement these if inferred from
RTL, but the result still consumes D-FF resources.
Can flip-flops be instantiated explicitly in RTL, or are they always inferred?
Both approaches are valid. In most
FPGA workflows, FFs are inferred from synchronous
RTL constructs (clocked always/process blocks), which is preferred for portability and readability. Explicit instantiation using vendor primitives (e.g., Xilinx FDRE or Intel DFF) is sometimes used when precise control over initialization, reset polarity, or clock-enable behavior is needed, or when a specific primitive must be placed to meet tight
timing constraints. Direct instantiation ties the code to a specific vendor or device family.
Differentiators vs similar concepts
Flip-flops are frequently confused with latches. The core distinction is edge-triggering (FF) versus level-sensitivity (
latch). In synchronous digital design, this matters enormously: latches have a transparent phase during which glitches on the input propagate directly to the output, complicating timing analysis. FFs sample only on the clock edge and are the standard storage element in synthesized
RTL. The terms are sometimes used interchangeably in casual speech, but the distinction is precise and important in any timing-sensitive or
FPGA context.
