A glitch is a spurious, unintended pulse or transient on a digital signal that occurs when combinational logic paths of different lengths cause intermediate incorrect output states before the circuit settles to its final value. Glitches are a direct consequence of propagation delay skew and are distinct from intentional signal transitions.
In practice
In combinational logic, glitches arise when multiple inputs to a gate change at slightly different times due to unequal path delays. For example, a simple AND gate fed by two signals derived from the same source through paths of different lengths may briefly see a 1-on-0 or 0-on-1 condition, producing a narrow spurious pulse at its output. In discrete TTL or CMOS glue logic, this is a frequent source of subtle bugs; in FPGAs the routing and LUT delays make glitch behavior even less predictable across synthesis tools or place-and-route runs.
Glitches become dangerous when they reach edge-sensitive inputs such as flip-flop clock pins, counter enables, latch enables, or interrupt lines. A glitch on a clock net can cause a flip-flop to capture data at the wrong time, corrupting state in ways that are difficult to reproduce. A glitch on a chip-select or write-enable line in a memory or peripheral bus can trigger an unintended write cycle. These failures are often intermittent and temperature- or voltage-dependent, making them hard to isolate without an oscilloscope or logic analyzer with high time resolution.
In FPGA and CPLD design, glitches are a well-known hazard discussed in resources like "FPGA Assemblers and Time Machines." A common mitigation is to register the outputs of combinational logic: routing combinational results through a flip-flop clocked by the system clock prevents glitches from propagating to the next synchronous stage, because the flip-flop only samples its input during the narrow setup/hold aperture around the clock edge, and glitches that occur and fully settle before that aperture are not captured. Note that registering outputs does not eliminate glitches within the combinational logic itself, and this approach is not always applicable to every output in a design. Hazard-free logic minimization (adding consensus terms to a Karnaugh map) can also eliminate static hazards in purely combinational paths, but this approach is rarely practical in large designs.
In security-sensitive embedded systems, glitches are also exploited intentionally. Voltage glitching and clock glitching are fault-injection techniques used to cause a microcontroller to skip instructions, misread memory, or bypass secure boot checks. Some devices in families such as the STM32, LPC55S, and ATECC608 include brownout detection, clock security systems, or tamper-response features that can help detect or respond to such attacks, though the specific protections vary by exact part number.
Frequently asked
How is a glitch different from metastability?
A glitch is a spurious pulse produced by combinational path delay
skew; it is a deterministic (though often timing-dependent) consequence of the logic structure.
Metastability occurs when a
flip-flop's setup or hold time is violated, leaving its output in an indeterminate analog state for an unpredictable duration. A glitch on a clock or data input can cause metastability, but the two phenomena are distinct: glitches are at the combinational level, metastability is at the sequential level.
Will a glitch always show up on a logic analyzer?
Not necessarily. Many logic analyzers sample at a fixed rate and will miss glitches narrower than their sample period. Some analyzers have a glitch-capture mode that triggers on pulses shorter than one sample clock. An oscilloscope with sufficient bandwidth is often more reliable for detecting narrow glitches on critical nets like clock or chip-select lines.
Does registering all outputs really eliminate glitches?
Registering outputs removes glitches from the perspective of downstream logic that is also clocked from the same domain, because the
flip-flop acts as a filter: glitches that occur and settle before the setup-time window are never captured. However, if the glitch itself occurs during the setup or hold window of the capturing flip-flop, it can still cause a wrong value to be latched. Proper static timing analysis (STA) in
FPGA or
ASIC flows ensures combinational paths settle well before the clock edge, which is why meeting timing closure is essential.
Are glitches a concern on microcontroller GPIO or peripheral buses?
Yes, particularly on asynchronous control signals such as chip-select, write-enable, or
latch-enable lines driven by combinational decode logic. A glitch on a write-enable can trigger an unintended write to a peripheral or external memory. Common mitigations include using registered address decode logic, adding RC filters on sensitive control lines (accepting the bandwidth trade-off), or using synchronous peripherals that only act on registered strobes.
What is the difference between a static hazard and a dynamic hazard?
A static hazard is a glitch that occurs when the output is supposed to remain constant: a static-1 hazard produces a brief 0 pulse on a line that should stay high, and a static-0 hazard produces a brief 1 pulse on a line that should stay low. A dynamic hazard occurs during an intended output transition: instead of making a single clean 0-to-1 or 1-to-0 transition, the output briefly oscillates (e.g., 0-1-0-1) before settling. Dynamic hazards typically appear in multi-level logic and are less common in two-level sum-of-products implementations.
Differentiators vs similar concepts
Glitch vs. runt pulse: a runt pulse is a pulse that does not reach a full logic threshold level (it is an amplitude problem), whereas a glitch is defined by its unintended occurrence and narrow width regardless of whether it fully crosses logic thresholds. In practice the terms are sometimes used loosely and interchangeably, but in oscilloscope trigger terminology they are separate conditions. Glitch vs. bounce: contact bounce on mechanical switches produces multiple transitions over milliseconds; a glitch in digital logic is typically nanoseconds to tens of nanoseconds wide and is caused by propagation delay
skew rather than mechanical effects.
