The Internal Configuration Access Port (ICAP) is a vendor-specific primitive available on Xilinx FPGAs that provides fabric-side read and write access to the device's configuration logic, allowing the running design itself to reconfigure parts of the FPGA or read back configuration data without an external host.
In practice
ICAP is the internal configuration access path, complementing external interfaces such as SelectMAP (a parallel configuration bus) and JTAG (a serial debug and configuration interface). Because it is accessible from within the FPGA fabric, a softcore processor or custom state machine can write a partial bitstream directly into the configuration engine at runtime. This is a common foundation of partial reconfiguration (PR) workflows on Xilinx 7-series, UltraScale, and UltraScale+ devices, where regions of the fabric are reconfigured while the rest of the device continues operating, though PR can also be driven through other configuration paths and tools.
A common pattern is to store partial bitstreams in external flash or DRAM and stream them through the ICAP primitive on demand. The soft processor (for example, a MicroBlaze or PicoBlaze core) reads the bitstream bytes and drives the ICAP data and control signals. Timing is critical: ICAP on 7-series devices operates at up to a maximum clock rate that varies by device and configuration details, but requires precise control of the CSB (chip select) and WRITE signals, and the byte ordering of the bitstream must match the port width (8 or 32 bits depending on the primitive variant used).
ICAP also supports configuration readback, which lets the design read the current state of configuration registers (including the IDCODE, status register, and frame data). This is used for scrubbing SEU (single-event upset) errors in radiation-tolerant designs, where the readback data is compared against a golden reference and any corrupted frames are rewritten.
A notable pitfall is byte-swapping: the bitstream byte order expected by ICAP differs from the raw binary order produced by Vivado or ISE by default. Failing to account for this swap is one of the most common reasons ICAP-based partial reconfiguration silently fails. Xilinx application note XAPP1100 and related documentation describe the required bit/byte reordering in detail.
Frequently asked
What is the difference between ICAP and JTAG/SelectMAP for FPGA configuration?
JTAG and SelectMAP are external interfaces driven by a host tool or processor outside the
FPGA. ICAP exposes equivalent configuration access to logic running inside the fabric. This makes ICAP the preferred path when the FPGA itself must manage its own
reconfiguration autonomously, without an external configuration controller.
Which Xilinx device families include ICAP?
ICAP is available on Xilinx Virtex-II Pro and later families, including Spartan-6, all 7-series (Artix-7, Kintex-7, Virtex-7), UltraScale, and UltraScale+. The primitive name varies by generation (for example, ICAPE2 on 7-series and ICAPE3 on UltraScale/UltraScale+); consult the relevant Xilinx/AMD Libraries Guide for the exact primitive name and port definitions for your target device. The register interface and supported commands differ slightly between generations.
Can a soft processor like PicoBlaze or MicroBlaze drive ICAP directly?
Yes. A soft processor can instantiate or interface to the ICAP primitive and write
bitstream data to it byte by byte or word by word. PicoBlaze, referenced in the blog post 'PicoBlaze - Program RAM Access for an Interactive Monitor', illustrates how fabric-accessible primitives can be driven from a small embedded softcore.
MicroBlaze is more commonly used for full
partial reconfiguration flows due to its 32-bit data path matching the ICAPE2/ICAPE3 port width.
What is the byte-swapping issue with ICAP?
Xilinx
bitstream files are generated with a specific byte order intended for SelectMAP or
JTAG interfaces. ICAP expects the nibbles or bytes within each 32-bit word to be reordered before being written to the port. On 7-series (ICAPE2), each byte within a 32-bit word must have its bits reflected (bit-reversed), and the byte order within the word must be swapped. Writing raw bitstream bytes to ICAP without this transformation produces a corrupted configuration frame and typically causes no visible error, just a silently wrong result.
Is ICAP available on Intel/Altera or Lattice FPGAs?
Not under that name. Intel FPGAs provide similar internal
reconfiguration capability through the PR (Partial Reconfiguration) IP and the PRBLOCK interface. Lattice FPGAs offer internal reconfiguration-related features through device-specific primitives and IP; refer to the relevant Lattice documentation for the primitives and programming model supported on your target device. The concept is broadly similar -- fabric logic drives a configuration engine -- but the primitives,
bitstream formats, and programming models differ significantly across vendors.
Differentiators vs similar concepts
ICAP is often compared to the SelectMAP interface. SelectMAP is an external parallel configuration bus driven by a host processor or configuration device outside the
FPGA; ICAP exposes the same configuration engine to logic inside the fabric. ICAP is also distinct from
JTAG-based configuration (driven externally via a debug cable) and from multiboot/fallback mechanisms (which trigger a full device
reconfiguration from a new
bitstream address), though ICAP can be used to initiate a multiboot sequence by writing the appropriate configuration commands.
