IOSTANDARD is an attribute or constraint applied to FPGA I/O pins that selects the electrical signaling standard (voltage level, termination behavior, and logic thresholds) for that pin. Setting the correct IOSTANDARD ensures that the FPGA's output drivers and input receivers are electrically compatible with the connected device.
In practice
In most FPGA toolflows (Xilinx/AMD Vivado and ISE, Intel/Altera Quartus, Lattice Diamond, etc.), IOSTANDARD is specified either in a pin constraints file (XDC, UCF, or QSF) or as an HDL attribute on a port. Common values include LVCMOS33, LVCMOS18, LVCMOS25, LVTTL, LVDS, and SSTL for DDR memory interfaces, though exact names and available standards vary by vendor and device family. The chosen standard must match the supply voltage of the I/O bank the pin belongs to, because FPGA I/O banks are typically powered by a dedicated VCCO rail. Assigning an LVCMOS33 standard to a bank powered at 1.8 V, for example, is an error the tools will flag or, in some cases, silently accept while producing hardware that may damage the device or fail to meet signal-integrity margins.
Differential standards such as LVDS or LVPECL generally require pairing a positive (P) and negative (N) pin, though some devices support pseudo-differential or AC-coupled variants, and pin-pairing conventions vary by vendor. Many toolchains enforce that both pins of the pair share the same differential IOSTANDARD and belong to a bank that supports differential signaling, though the exact enforcement rules and bank requirements differ by vendor and device family. Single-ended standards like LVCMOS are far more common for general-purpose GPIO, SPI, UART, and similar interfaces at moderate frequencies.
Drive strength and slew rate settings frequently accompany IOSTANDARD. For example, an LVCMOS33 pin might additionally specify DRIVE 8 and SLEW SLOW to reduce EMI on a low-frequency control line, or DRIVE 16 and SLEW FAST for a high-speed data bus. These sub-attributes do not change the voltage standard itself but affect the output impedance and switching behavior of the driver.
Failing to specify an IOSTANDARD forces the toolchain to apply a default, which varies by vendor, device family, and bank supply voltage. On Xilinx 7-series and UltraScale devices, the tool may infer a standard from the bank VCCO or require an explicit constraint depending on the flow and bank configuration; a fixed default should not be assumed. Relying on defaults in production designs is risky regardless. Explicit constraints prevent silent mismatches when a design is retargeted to a different device or board revision. Blog posts like "The Spartans" and "Learning VHDL - Basics" illustrate how FPGA I/O configuration fits into a complete design flow on Xilinx Spartan-class parts.
Frequently asked
Where do I set IOSTANDARD in a Xilinx/AMD Vivado design?
The most common place is the
XDC constraints file, using a line such as: set_property IOSTANDARD LVCMOS33 [get_ports {my_signal}]. You can also apply it as a
VHDL or
Verilog attribute directly on the port declaration, or set it interactively in the
Vivado I/O Planner GUI. All three methods are merged by the tools into the design database and produce equivalent results in the implemented design, though they may be represented differently at intermediate stages of the flow.
What happens if IOSTANDARD does not match the bank supply voltage (VCCO)?
On most Xilinx 7-series and UltraScale devices,
Vivado will issue a DRC error or critical warning and refuse to generate a
bitstream. On older tools or some other vendor flows the mismatch may slip through to hardware, where it can cause input threshold violations, excessive current draw, or, in severe cases, damage to the I/O buffer. Always verify the VCCO rail on your PCB matches every IOSTANDARD assigned to pins in that bank.
Is IOSTANDARD an FPGA-specific concept, or does it appear on MCUs too?
It is primarily an
FPGA concept. MCU datasheets describe compatible voltage levels and drive strengths per pin, but they rarely expose a single user-selectable 'IOSTANDARD' attribute. FPGAs use configurable I/O banks with programmable drivers and receivers, so a unified constraint attribute is necessary. On MCUs, the equivalent information is typically a fixed characteristic listed in the electrical specifications table.
Can two pins in the same I/O bank use different IOSTANDARD values?
Pins in the same bank can use different single-ended standards as long as they all require the same VCCO supply voltage. For instance, LVCMOS33 and LVTTL can often coexist in a 3.3 V bank because both operate at 3.3 V. Mixing standards that require different VCCO values in one bank is not allowed on most
FPGA architectures; the toolchain will flag it as a bank-compatibility violation.
What IOSTANDARD should I use for an LVDS interface?
Use
LVDS (or LVDS_25 on older Xilinx devices) for on-chip LVDS-capable banks. Assign it to the differential pair together, e.g., set_property IOSTANDARD LVDS [get_ports {clk_p clk_n}]. Some
FPGA families require DIFF_TERM TRUE to enable the on-chip 100-ohm differential
termination; without it you may need an external termination resistor to meet the LVDS specification. Check the I/O bank type in your device datasheet, as not all banks support differential standards.
Differentiators vs similar concepts
IOSTANDARD defines the electrical protocol family (voltage level and signaling convention) for a pin, while DRIVE and SLEW are separate attributes that tune output current strength and switching speed within a given standard. Confusing IOSTANDARD with
DRIVE strength is common: changing DRIVE from 4 mA to 16 mA does not change the voltage standard from LVCMOS18 to LVCMOS33. A related source of confusion is VCCIO vs. VCCO vs. VREF: VCCO and VCCIO are both names used for the physical supply to the I/O bank, though the exact naming convention differs by vendor and device family; IOSTANDARD is the software constraint that must match that supply; and VREF is an optional external reference voltage required only by certain standards such as SSTL and HSTL.
