Xilinx ISE (Integrated Software Environment) is Xilinx's legacy FPGA/CPLD design suite, covering HDL entry, synthesis, implementation (mapping, place-and-route), bitstream generation, and on-chip debugging for specific older device families. It was superseded by Xilinx Vivado for newer 7-series and UltraScale parts, but remains the required toolchain for older families such as Spartan-3/6 and Virtex-4/5/6.
In practice
ISE is the tool you will reach for when working with Xilinx FPGAs and CPLDs predating the 7-series: Spartan-3, Spartan-6, Virtex-4, Virtex-5, Virtex-6, and the CoolRunner CPLD families, among others. It bundles several sub-tools under one GUI: XST (synthesis), NGDBuild/MAP/PAR (implementation), BitGen (bitstream generation), and iMPACT (device programming). The blog post "The Spartans" covers Spartan-family devices that rely on ISE for their full toolchain support.
The ISE Project Navigator GUI is the most common entry point, but many teams automate builds using Tcl scripts or Makefiles that invoke the individual command-line executables directly. The blog post "Makefiles for Xilinx Tools" demonstrates this approach. Running ISE headlessly is straightforward because each stage (xst, ngdbuild, map, par, bitgen, trce) is a standalone executable that accepts a project or options file.
For simulation, ISE ships with ISim, its built-in HDL simulator, which handles basic functional and timing simulation without a separate license. More demanding workflows often substitute ModelSim or XSIM (the Vivado-era simulator). The posts "How to start in FPGA development? - Simulation software tools" and "Learning VHDL - Basics" are relevant for beginners setting up an ISE-based HDL simulation flow.
A common pitfall is OS compatibility: ISE 14.7 (the final release, from 2013) officially supports Windows 7 and select Linux distributions. Running it on modern Linux requires workarounds for library dependencies, and native support on Windows 10/11 is unofficial. Xilinx has at times distributed a VM image to ease this, but users should expect some environment friction on contemporary host systems.
Discussed on FPGARelated
Frequently asked
Which Xilinx device families require ISE instead of Vivado?
ISE is required for Spartan-3, Spartan-6, Virtex-4, Virtex-5, Virtex-6, CoolRunner, and CoolRunner-II families.
Vivado does not support these parts. Xilinx 7-series devices (Spartan-7, Artix-7, Kintex-7, Virtex-7) and most later families use Vivado, though tool support for specific devices should always be confirmed against Xilinx's official support documentation. The blog post 'The Spartans' discusses the Spartan-family context.
What is the last version of ISE, and is it still available?
ISE 14.7, released in October 2013, is the final version. Xilinx (now AMD) still makes it available for download from their support site, though active development ended with that release. A pre-configured virtual machine image has also been offered at various points to sidestep OS compatibility issues on modern hosts, though availability of this packaging may vary over time.
Can ISE builds be automated without the GUI?
Yes. Each ISE stage has a corresponding command-line tool (xst, ngdbuild, map, par, bitgen, trce, impact). These can be driven by Tcl scripts, shell scripts, or Makefiles. The blog post 'Makefiles for Xilinx Tools' walks through structuring such a build system.
What simulator is included with ISE, and what are its limitations?
ISE includes ISim, which generally supports functional and post-route timing
simulation for
VHDL,
Verilog, and mixed-language designs, though specific capabilities can depend on the ISE version and flow being used. ISim is adequate for many educational and moderate-complexity projects, but it is slower and less feature-rich than commercial simulators like ModelSim. The post 'How to start in
FPGA development? - Simulation software tools' compares simulation options relevant to ISE users.
How does ISE handle on-chip debugging?
ISE integrates ChipScope Pro (now called
ILA/VIO in
Vivado terms), which inserts logic analyzer and virtual I/O cores into the design
netlist. These cores communicate over
JTAG at runtime, allowing signal capture without external probes. ChipScope requires an additional license in some configurations, though free tiers with core-count limits have been available.
Differentiators vs similar concepts
ISE is often confused with Xilinx
Vivado, its successor. The split is device-driven: ISE targets pre-7-series families (Spartan-3/6, Virtex-4/5/6, CoolRunner CPLDs); Vivado targets 7-series and newer. Vivado uses a different
synthesis engine (Vivado Synthesis, replacing XST), a different implementation flow, and a different project file format -- ISE projects are not directly importable into Vivado. ISE also ships with ISim, whereas Vivado uses XSIM. For Zynq-7000 SoCs, Vivado is the required tool even though Zynq carries an ARM Cortex-A9, which underscores that the tool boundary is by device family, not by whether the part contains a processor.
