Jitter is the variation in the timing of a periodic signal or event relative to its ideal, expected position in time. It is measured as a deviation -- typically in nanoseconds or picoseconds -- from a reference edge, clock tick, or deadline.
In practice
In digital systems, jitter appears on clock lines, communication signals, PWM outputs, and interrupt service routine (ISR) entry times. On a clock signal, jitter manifests as cycle-to-cycle variation in period or edge placement. On a clocked serial bus like SPI, excessive jitter on the clock can cause receivers to sample at the wrong point, leading to bit errors; on a UART, which has no separate clock line, the analogous concern is baud-rate mismatch and sampling uncertainty rather than clock jitter on the bus. In PWM generation, jitter on the output edges translates directly to noise in motor control or audio applications.
ISR latency jitter is a common concern in bare-metal and RTOS-based firmware. Even if a timer fires deterministically, the time from interrupt assertion to the first instruction of the ISR can vary due to instruction pipeline stalls, cache misses (on Cortex-A or Cortex-M7/M55 cores with cache), interrupt priority arbitration, or DMA bus contention. On simpler 8-bit MCUs like AVR or PIC, jitter is smaller but still exists due to multi-cycle instructions that must complete before the CPU responds to an interrupt.
Jitter is categorized in several ways. Cycle-to-cycle jitter is the period variation between adjacent cycles. Accumulated (or long-term) jitter is the deviation measured over many cycles. Phase jitter refers to the instantaneous phase error relative to an ideal reference. In communications, there is also a distinction between deterministic jitter (caused by identifiable sources such as crosstalk or inter-symbol interference) and random jitter (caused by thermal noise and other stochastic processes).
Reducing jitter typically requires a combination of hardware and software techniques: using a phase-locked loop (PLL) or delay-locked loop (DLL) to clean up a noisy reference clock, keeping critical ISRs short and at the highest priority, disabling interrupts around time-sensitive operations (with care for overall latency), and filtering measured timestamps -- for example with a running average as discussed in the "Running Average" post. For applications requiring tight frequency lock to an external reference such as GPS 1PPS, a software DPLL approach (as described in "Use DPLL to Lock Digital Oscillator to 1PPS Signal") can actively correct accumulated phase error.
Frequently asked
What is the difference between jitter and latency?
Latency is the absolute delay between a trigger and a response -- for example, the time from an interrupt assertion to ISR entry. Jitter is the variation in that delay across multiple occurrences. A system can have high latency but low jitter (predictable but slow response) or low latency but high jitter (fast on average but inconsistent). Real-time systems often care more about minimizing jitter than minimizing average latency.
How is jitter measured in practice on an embedded target?
A common method is to toggle a GPIO at the event of interest (timer ISR entry, task start, etc.) and capture the resulting waveform on an oscilloscope. Persistence mode or histogram mode reveals the spread of edge timing. For finer measurement, a logic analyzer with timestamp resolution of a few nanoseconds or a dedicated time-interval counter can be used. Software-only measurement using a free-running hardware timer to record timestamps and then computing the variance is also practical, though the measurement itself adds some overhead.
What causes ISR jitter on a Cortex-M MCU?
On ARM Cortex-M cores, the dominant sources of ISR entry jitter include: the latency of completing an ongoing multi-cycle instruction (e.g., a load-multiple LDMIA can stall entry by several cycles), tail-chaining or late-arrival interrupt stacking, flash wait states if the vector table or ISR code is not in RAM or cache, and bus contention with DMA. On Cortex-M cores with an instruction cache (M7, M55), cache miss penalty also contributes. Hardware stacking of the exception frame takes a fixed 12 cycles on most Cortex-M implementations when there is no bus contention, so that portion does not add variable jitter.
Does an RTOS make jitter worse compared to bare-metal?
It can. An RTOS introduces additional sources of jitter: scheduler execution time, critical sections that mask interrupts (common in many FreeRTOS ports around queue and semaphore operations), and tick-based wakeup granularity. A task waiting on an RTOS delay will typically wake up up to nearly one full tick period after the requested delay (e.g., up to ~1 ms late at a 1 kHz tick rate) plus scheduler overhead, depending on the RTOS API and tick alignment. For tight timing requirements, it is common to handle the time-critical portion directly in an ISR rather than in a task, even when using an RTOS.
How much jitter is acceptable on a serial bus like UART?
UART has no separate clock line; both ends derive timing from their own oscillators. The receiver samples each bit near the center of the bit period. The tolerable timing budget depends on oversampling ratio, frame length, baud-rate error on both ends, and receiver design, but as a rough rule of thumb many UART receivers begin to see sampling errors when the combined clock accuracy and jitter budget exceeds roughly 3 to 5 percent of the bit period. At 115200 bps, one bit period is about 8.7 us, so the total timing error across a frame must stay well within roughly 400 ns. RC oscillators on low-cost MCUs (often 1 to 2 percent accuracy without calibration) consume most of this budget, leaving little room for additional jitter.
Differentiators vs similar concepts
Jitter is often confused with phase noise and with latency. Phase noise is the frequency-domain representation of timing variation -- a signal with high jitter tends to exhibit high phase noise, and vice versa, but the two are related views rather than identical measures: converting between them depends on the offset-frequency band and the integration method. Phase noise is expressed as power spectral density (dBc/Hz at a given offset frequency) and is the preferred metric in RF and clock-distribution contexts, while jitter is the preferred time-domain metric in digital and embedded work. Latency, as noted above, is the absolute delay to an event; jitter is the variation in that delay. Wander is a related term used in telecom standards to describe very low-frequency phase variation (below 10 Hz), distinguishing it from jitter which covers higher-frequency variation.
