A latch is a level-sensitive bistable storage element that is transparent to its input while an enable signal is asserted, and holds its last captured value when the enable is deasserted. Unlike a flip-flop, a latch has no clock edge; it responds continuously to its inputs during the active enable phase.
In practice
In digital logic design, latches appear in two main contexts: intentional and unintentional. Intentional latches are used where level-sensitive behavior is genuinely needed, such as in certain bus-hold circuits, transparent data paths, or timing-critical paths where a half-cycle of extra propagation time is useful. In FPGA fabrics, the basic storage primitive is typically a flip-flop (e.g., the Spartan-6 uses D-type flip-flops inside its slices), so a latch inferred from HDL often consumes a LUT configured to emulate latch behavior rather than a dedicated latch primitive, though the exact mapping depends on the vendor, device family, and synthesis tool. This can complicate timing analysis.
Unintentional latch inference is a common pitfall in VHDL and Verilog. If a combinational process or always block does not assign an output signal under every possible branch of its conditional logic, most synthesis tools will infer a latch to hold the previous value for the undriven cases, though the exact behavior can depend on coding style and tool. This typically happens when an if/else construct lacks a final else clause, or a case statement omits a default. Inferred latches are often flagged as warnings by synthesis tools (Vivado, Quartus, Synplify) and are considered a design defect in synchronous designs because they are difficult to time, can cause hold-time violations, and may behave differently in simulation versus silicon.
On ASIC and structured ASIC flows, level-sensitive latches do appear as deliberate standard-cell primitives (e.g., the widely used SR latch, the D-latch with enable, and transparent low/transparent high variants). High-performance ASIC pipelines sometimes use latch-based (time-borrowing) pipelines intentionally to recover timing slack across stage boundaries, but this requires careful static timing analysis and is rarely done in FPGA-based designs.
For embedded firmware developers working above the gate level, the practical takeaway is to write HDL with complete assignments in every combinational block to avoid accidental latch inference, and to treat synthesis warnings about inferred latches as errors until each one is deliberately reviewed and justified.
Frequently asked
What is the difference between a latch and a flip-flop?
A latch is level-sensitive: its output follows its input whenever the enable is active. A
flip-flop is edge-sensitive: it captures input only on a rising or falling clock edge. In synchronous designs, flip-flops are almost always preferred because their timing behavior is well-defined and more straightforward to analyze with standard STA tools than the transparency-window analysis required for latches.
Why does my synthesis tool warn about an inferred latch?
A latch is inferred when
combinational logic does not define an output for every possible input combination, so the synthesizer must hold the previous value somehow. The most common cause is an if statement without a matching else, or a case statement without a default, inside a combinational process or always block. Adding the missing branch (or assigning a default value at the top of the block) eliminates the latch.
Are latches ever acceptable in FPGA designs?
Occasionally, but they require explicit justification. On many Xilinx and Intel/Altera FPGAs, a latch may be implemented inside a
LUT or mapped to a dedicated (and often limited) latch primitive, though availability and exact implementation vary by device family and generation. Either way, this complicates static timing analysis. Using LUTs for latches rather than logic or
flip-flops is usually a sign of an
HDL coding problem rather than a deliberate optimization.
What is an SR latch, and how does it relate to a D-latch?
An SR (Set-Reset) latch has two inputs: S forces the output high, R forces it low, and both deasserted holds the previous state. The forbidden state (S=1, R=1) produces undefined or implementation-dependent behavior. A D-latch adds an enable and derives S/R from a single data input, removing the forbidden state and making it more practical as a general storage element.
Can a race condition occur inside a latch?
Yes. Because a latch is transparent while enabled, glitches on the data or enable inputs can propagate directly to the output or cause the latch to toggle unexpectedly. This is one reason synchronous designers avoid latches: a clocked
flip-flop samples only at the clock edge, so short glitches between edges are ignored, whereas a latch has no such rejection window.
Differentiators vs similar concepts
A latch is often confused with a
flip-flop. The key distinction is sensitivity: a latch responds to its input level continuously while enabled (level-triggered), whereas a flip-flop responds only at the active edge of a clock signal (edge-triggered). In synchronous digital design, "register" almost always refers to a flip-flop, not a latch. The two also differ in timing analysis: flip-flop setup and hold times are referenced to a clock edge, while latch timing involves a transparency window that requires more complex analysis. In
HDL, accidentally writing
combinational logic that infers a latch instead of a register is one of the most common
synthesis mistakes for new designers.
