LVDS (Low-Voltage Differential Signaling) is a high-speed, low-power electrical signaling standard that transmits data as a small voltage difference (typically 350 mV) between two complementary signal lines, rather than as a voltage referenced to ground. The differential nature makes it highly immune to common-mode noise and allows signaling at hundreds of Mbps to several Gbps over copper traces or cables.
In practice
LVDS appears most often in embedded systems as the physical layer for high-bandwidth point-to-point links: camera interfaces (MIPI CSI derivatives, Camera Link), flat-panel display interfaces (FPD-Link, OpenLDI/OLDI driving TFT-LCDs), FPGA-to-FPGA links, and high-speed ADC/DAC data buses. Many FPGAs (Xilinx Spartan-6, Kintex-7, Intel Cyclone V, Lattice ECP5) include dedicated LVDS I/O buffers and serializers (SERDES) that can operate at several hundred Mbps to several Gbps per pair, making LVDS a natural choice for moving large amounts of pixel or sample data off-chip.
On microcontroller-class devices, native LVDS I/O is less common. Some high-end SoCs (e.g., NXP i.MX series, Renesas RZ/G) integrate LVDS display serializers specifically for driving parallel RGB TFT panels via a thin, noise-resistant cable. In these designs LVDS is typically used only at the display output stage; the rest of the system uses single-ended CMOS signaling internally.
A key practical constraint is termination: LVDS receivers require a 100-ohm differential termination resistor placed as close to the receiver as possible. Omitting or misplacing it causes reflections that corrupt signals at even moderate data rates. PCB layout discipline matters -- matched-length, tightly coupled differential pairs with controlled 100-ohm differential impedance are required, and any length mismatch between the P and N conductors of a pair (skew) degrades the received eye diagram.
LVDS defines only the electrical layer, not a protocol. Protocols and interface families such as FPD-Link, Camera Link, and JESD204B use LVDS as their physical layer, but the framing, encoding (often 8b/10b or similar), and link training are defined by those higher-level specifications, not by LVDS itself. When debugging an LVDS link, the usual first checks are: correct termination present, differential impedance on the board matched to 100 ohms, pair skew within spec, and common-mode voltage within the receiver's input range (typically 1.0 to 1.4 V for standard LVDS receivers).
Discussed on FPGARelated
Frequently asked
What voltage swing does LVDS use, and why is it so small?
Standard LVDS (TIA/EIA-644) specifies a differential output swing of nominally 350 mV (minimum 250 mV, maximum 450 mV) centered around a common-mode voltage of approximately 1.2 V. The small swing reduces power consumption (less charge moved per transition) and limits electromagnetic emissions. Because the receiver responds only to the difference between the two conductors, common-mode noise injected equally onto both lines cancels out, making the link robust despite the low swing.
Do I need external termination resistors for LVDS?
Yes, in almost all cases. A 100-ohm resistor placed differentially at the receiver end is required to absorb the transmission-line wave and prevent reflections. Some
FPGA I/O blocks and dedicated LVDS receiver ICs include an optional internal
termination, but external placement close to the receiver pins is generally preferred for signal integrity. Forgetting termination is one of the most common LVDS bring-up mistakes.
How fast can LVDS go?
Standard LVDS electrical signaling (TIA/EIA-644) supports data rates up to roughly 655 Mbps per differential pair. In practice, many
FPGA SERDES primitives using LVDS-compatible I/O standards operate at 1 Gbps and beyond per lane (e.g., Xilinx Spartan-6 LVDS at up to 1 Gbps, Kintex-7 transceivers at multi-Gbps), though those higher-speed variants often use enhanced driver/receiver circuits that exceed the original standard's scope. The achievable rate on a given board is ultimately constrained by PCB trace quality, pair matching, cable length, connector quality, receiver tolerance, and the specific I/O cell characteristics, as well as any encoding overhead imposed by the protocol layer.
What is the difference between LVDS and MIPI D-PHY or MIPI DSI?
LVDS and MIPI D-
PHY are different electrical standards that serve similar purposes. MIPI D-PHY (used by DSI for displays and CSI-2 for cameras) uses a low-swing differential pair like LVDS but operates in multiple modes on the same wires: a high-speed (HS) differential mode for bulk data transfer and one or more low-power (LP) modes that use the lines in a single-ended fashion for control signaling, with defined escape sequences and lane-state transitions between them. MIPI D-PHY is a controlled, multi-layer standard with defined lane management and is ubiquitous in mobile/embedded SoCs. Classic LVDS (FPD-Link, OLDI) is simpler and more common in industrial displays and
FPGA designs. They are electrically and logically incompatible; you cannot connect a MIPI DSI source directly to a raw LVDS receiver.
Can I implement LVDS on an FPGA without dedicated LVDS I/O buffers?
Not reliably at high speed. FPGAs with dedicated LVDS I/O cells (e.g., Xilinx Spartan-6, Intel Cyclone V, Lattice ECP5) instantiate purpose-built differential drivers and receivers that meet TIA/EIA-644 electrical specs. Attempting to mimic LVDS using standard CMOS I/O toggled by fabric logic will produce single-ended outputs with wrong voltage levels and will not satisfy the differential impedance and common-mode requirements that LVDS receivers expect. Some low-speed, loosely coupled differential schemes are possible with CMOS I/O, but they are not LVDS.
Differentiators vs similar concepts
LVDS is often confused with several related differential standards. RS-485 is also differential but targets multi-drop bus topologies at lower speeds (the practical upper limit varies widely by device and layout, with many datasheets citing figures in the tens of Mbps) with much higher
drive strength; LVDS is intended for point-to-point links and is generally not suitable for driving an RS-485 multi-drop bus. MIPI D-
PHY (used in DSI/CSI-2) uses a similar low-swing differential pair concept but adds defined high-speed and low-power operating modes on the same wires, lane management protocol, and escape sequences -- it is a full electrical and link-layer specification rather than a bare signaling standard. LVPECL is another differential standard common in clock distribution; it uses a different common-mode voltage (around 2 V below VCC) and typically requires AC coupling or DC
termination to a specific voltage, making it electrically incompatible with LVDS receivers without a translator. SLVS (Scalable Low-Voltage Signaling), used in some Sony sensor interfaces and JEDEC standards, uses an even smaller swing (as low as 100 mV differential) and is not interchangeable with standard LVDS.
