A Mixed-Mode Clock Manager (MMCM) is a clock synthesis and conditioning block found in certain Xilinx FPGA families that generates, multiplies, divides, phase-shifts, and deskews clock signals on-chip. It combines the capabilities of a PLL with additional features such as fractional clock division (on select outputs) and fine-grained phase adjustment. Exact feature availability varies by device family and speed grade; always consult the clocking resources section of the target device datasheet.
In practice
In most Xilinx 7-series, UltraScale, and UltraScale+ designs, the MMCM is the primary resource for generating derived clocks from an incoming reference. A single MMCM can accept one reference clock and produce up to seven independent output clocks (CLKOUT0 through CLKOUT6 on 7-series parts). On 7-series parts, fractional division is available only on CLKOUT0 (and the feedback output CLKFBOUT); CLKOUT1 through CLKOUT6 support integer division only. Each output has its own divide ratio and phase offset. This lets a single 200 MHz board oscillator fan out to, say, a 100 MHz system bus clock, a 50 MHz peripheral clock, and a 400 MHz memory interface clock all from one primitive.
A key use case is meeting setup and hold timing across clock domains. The MMCM's deskew capability uses the feedback path and internal compensation modes to align the output clock edge at an FPGA I/O pin tightly with the reference edge. This is essential for source-synchronous interfaces such as DDR, LVDS capture, and high-speed SERDES alignment. Phase shift can be set statically in the constraints file or adjusted dynamically at runtime in fine-phase-shift mode (typically 56 ps per step on 7-series), which some designs use to calibrate interface timing after power-up.
A common pitfall is violating the MMCM's input frequency range. On Xilinx 7-series devices the VCO frequency must stay within a rated range that varies by device and speed grade; consult the clocking resources table in the specific device datasheet for exact limits rather than relying on generic figures. Choosing multiply and divide values that push the VCO outside its rated range causes the MMCM to fail to lock, which can be a subtle bug if the LOCKED output is not monitored. Vivado's Clocking Wizard IP handles this automatically, but hand-instantiated MMCMs require manual verification.
Another common issue is forgetting to use BUFG or BUFGCE primitives on MMCM outputs that drive global clock networks. Without a clock buffer, the output may reach only a subset of the fabric or exhibit higher skew than expected. Some designs also neglect to assert a reset after power-up or after a reference clock glitch; while many MMCM configurations will lock without an explicit reset, the Xilinx documentation recommends asserting RST for at least one reference clock cycle when the reference is unstable.
Frequently asked
What is the difference between an MMCM and a PLL in Xilinx FPGAs?
Both primitives use a voltage-controlled
oscillator and feedback loop to synthesize clocks. The MMCM adds fractional divide capability on CLKOUT0 (allowing non-integer M/D ratios on that output), fine-phase-shift mode for dynamic phase adjustment, and spread-spectrum input support on certain devices.
PLLs in 7-series and UltraScale parts are smaller, have fewer output ports (typically six versus seven), and lack fractional division. The exact feature differences are device-dependent, so check the clocking resources section of your target datasheet. Use a PLL when resources are tight and you do not need the extra features; use an MMCM when you need fractional frequencies or dynamic phase control.
How do I know if my MMCM has locked?
The MMCM exposes a LOCKED output port that goes high once the output clocks are stable and within specification. In practice, system logic that depends on the MMCM output should be held in reset until LOCKED is asserted. On 7-series parts, lock typically takes on the order of a few microseconds after a valid reference is present, but the exact time depends on the VCO frequency and loop filter settings. Failing to use LOCKED as a reset qualifier is a common source of intermittent startup failures.
Can I change the MMCM output frequency at runtime?
Yes, in two ways. Fine-phase-shift mode (CLKFBOUT_USE_FINE_PS or CLKOUT_USE_FINE_PS attributes) lets you shift the phase of a selected output by one VCO tap at a time (typically about 56 ps per step on 7-series -1 parts) without losing lock. For coarser changes, Xilinx provides the Dynamic
Reconfiguration Port (DRP), a register-mapped interface through which software or an
FSM can rewrite the MMCM's divide and multiply registers while it is running. The MMCM will lose lock during a DRP reconfiguration and must reacquire it before the new clocks are used.
Does the MMCM exist in Xilinx Spartan or Artix devices?
MMCM availability depends on the specific device family and part. Many 7-series devices including Artix-7, Kintex-7, Virtex-7, and Spartan-7 include MMCMs, but the count and exact features vary by part; not every part in a family is guaranteed to have the same clocking resources. Older families such as Spartan-6 use a different primitive called the DCM (Digital Clock Manager) and a separate
PLL; those do not have an MMCM. Always check the clocking resources section of the device datasheet for the exact primitive types and counts on your target part.
Should I instantiate the MMCM primitive directly or use Vivado's Clocking Wizard?
For most designs, the Clocking Wizard IP is the safer starting point. It validates that your requested frequencies keep the VCO within its legal range, generates the correct
BUFG connections, and produces a LOCKED-based reset synchronizer. Direct instantiation is reasonable when you need fine control over attributes the wizard does not expose, when you are migrating an existing design, or when you want to minimize IP dependencies in a tool-agnostic project. If you instantiate directly, cross-check your M, D, and O divider values against the MMCM
timing constraints in the device datasheet.
Differentiators vs similar concepts
MMCM vs.
PLL (Xilinx): Both synthesize clocks using a VCO and feedback divider, but the MMCM supports fractional output division on CLKOUT0, fine-phase-shift mode for dynamic phase trimming, and spread-spectrum reference inputs on supported devices. These features are not universally identical across all Xilinx families, so verify availability in the target device datasheet. Xilinx PLLs are a smaller, lower-resource primitive suited to simpler frequency
synthesis when those extra features are not needed. MMCM vs. DCM (older Xilinx families): The DCM (Digital Clock Manager) was used in certain older device families such as Spartan-3, Spartan-6, and Virtex-4/5, though availability varied by generation and subtype; it is not interchangeable with the MMCM and uses a different architecture and attribute set.
