A PHY (Physical Layer) is a hardware block that implements the electrical, optical, or radio-frequency signaling required to transmit and receive data on a physical medium. It sits at the boundary between the digital logic of an SoC or FPGA and the analog world of the wire, fiber, or wireless channel.
In practice
In embedded systems, the term PHY most commonly refers to a dedicated IC or integrated peripheral block that handles low-level signaling for interfaces such as Ethernet (e.g., the LAN8720, KSZ8081, or DP83867), USB, MIPI (camera and display), SATA, PCIe, or HDMI. Depending on the interface architecture, the PHY may handle tasks such as serialization/deserialization (SerDes), clock recovery, analog signal conditioning, and equalization; line encoding (e.g., 8b/10b or 64b/66b) is sometimes handled by a separate PCS (Physical Coding Sublayer) block rather than the PHY itself. The host SoC or FPGA communicates with a discrete Ethernet PHY over a standardized digital interface such as MII, RMII, or RGMII; SGMII is also used in some designs, particularly where a serial connection to the MAC is preferred, keeping the sensitive analog circuitry off the main die.
Many modern SoCs integrate the PHY on-chip alongside the MAC or controller. For example, certain STM32H7 and i.MX RT variants include a USB PHY on-die (though the specific USB speeds supported and any external component requirements vary by part number), while Ethernet PHYs are more commonly external discrete parts connected via RMII or RGMII. FPGAs such as those in the Xilinx UltraScale+ or Intel Stratix families embed multi-gigabit transceiver (MGT/SERDES) PHY blocks capable of running PCIe, 10GbE, or custom serial protocols at very high per-lane rates; the exact maximum rate depends on the specific device variant within each family.
A common pitfall is confusing the PHY with the MAC (Media Access Controller). The PHY deals strictly with bit-level signaling; the MAC handles framing, addressing, and flow control. Another frequent issue is power supply sensitivity: PHY blocks, especially high-speed SerDes, require clean, well-decoupled supplies and careful PCB layout (controlled impedance, differential pair matching) to meet eye diagram and jitter specifications. Ignoring vendor layout guidelines for a Gigabit Ethernet PHY or a USB 3.x PHY is a leading cause of intermittent link failures during hardware bring-up.
Register-level configuration of a discrete Ethernet PHY typically happens over an MDIO/MDC bus (a two-wire, half-duplex serial management interface defined in IEEE 802.3). Auto-negotiation, link speed, duplex mode, and energy-efficient Ethernet settings are all controlled through PHY registers. Drivers must poll or interrupt on the PHY's link-status register and often need to handle vendor-specific extended registers beyond the IEEE 802.3 standard set.
Frequently asked
What is the difference between a PHY and a MAC?
The MAC (Media Access Controller) handles framing, addressing, error detection, and flow control at the data-link layer. The PHY sits one layer below and deals purely with the physical transmission of bits: serialization, line encoding, clock recovery, and analog signal conditioning. In a typical Ethernet design, the MAC lives inside the SoC or
FPGA and talks to an external PHY chip over a digital interface like RMII or RGMII.
Do I always need an external PHY chip?
Not always. Many SoCs integrate USB PHYs on-die. However, Ethernet PHYs are frequently external because integrating analog RF/signal-conditioning circuitry alongside dense digital logic is costly and introduces noise coupling challenges. High-speed interfaces like PCIe and SATA on application-class SoCs often use embedded SerDes PHY blocks inside the chip, while board-level PHY ICs are still common for Gigabit and 10GbE Ethernet in embedded designs.
What is MDIO and why does it matter for Ethernet PHY bring-up?
MDIO (Management Data Input/Output), paired with a clock signal MDC, is the two-wire serial management interface defined in IEEE 802.3 for configuring and monitoring Ethernet PHY registers. During bring-up, you read the PHY identifier registers (registers 2 and 3) to confirm the part is alive and accessible, then configure link speed, duplex, and auto-negotiation settings. Failure to detect the PHY over MDIO usually points to a power, reset, or address-strapping problem before any Ethernet traffic is attempted.
What is the role of a PHY in USB designs?
A USB PHY converts the digital data from the USB controller (device or host) into the differential signaling (D+/D-) on the bus, handling the analog front-end functions including SE0 conditions and chirp sequences for high-speed negotiation. Functions such as bit stuffing and NRZI encoding are typically implemented in the USB controller or serial interface logic rather than in the PHY itself. Full-speed (12 Mbps) and low-speed (1.5 Mbps) PHYs are integrated into virtually all modern MCUs with USB. High-speed (480 Mbps) USB PHYs are integrated in higher-end MCUs like certain STM32H7 series and NXP i.MX RT parts, but may be external (ULPI-connected) in lower-cost or
FPGA-based designs.
Why is PCB layout so critical for high-speed PHY interfaces?
PHY transceivers operate on analog electrical principles even when the system appears digital. Differential pairs must be length-matched (typically within a few mils for multi-gigabit links), routed with controlled impedance (commonly 85-100 ohms differential for most protocols), and kept away from noisy signals. Stubs, vias, and layer transitions introduce reflections that degrade the eye diagram. Discrete Ethernet PHYs like the TI DP83867 and Microchip KSZ8081 include detailed layout guidelines in their datasheets; deviating from them is a frequent source of failed compliance testing and intermittent link drops.
Differentiators vs similar concepts
PHY vs. MAC: These two are frequently conflated. The PHY is responsible for the physical-layer signal (bits on wire); the MAC is responsible for the data-link layer (frames, addresses, flow control). In an Ethernet subsystem, both are required, and they communicate over a standardized digital interface (MII/RMII/RGMII/SGMII). Some devices integrate both (e.g., a single-chip Ethernet controller with internal MAC and PHY), but in most embedded Ethernet designs they are separate blocks, sometimes separate chips. PHY vs. SerDes: SerDes (serializer/deserializer) refers specifically to the serialization and deserialization function, which is one part of what a PHY does. A full PHY also includes clock and data recovery (CDR), equalization, line coding, and analog front-end circuitry. In
FPGA documentation, the embedded high-speed transceiver blocks are often called SerDes, SERDES, or GTX/GTH/GTP, but they functionally serve as PHY layers for protocols like PCIe, Ethernet, and SATA.
