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RLOC

Category: Configuration | Also known as: Relative Location

RLOC (commonly expanded as Relative LOCation) is an FPGA placement constraint that specifies the position of a logic element relative to other elements within the same user-defined group, rather than as an absolute fabric coordinate. It is primarily used to control the physical placement of related logic so that the tools preserve a desired topology while still allowing the group to be placed anywhere on the device, subject to legal resource availability and family-specific placement rules.

In practice

In Xilinx FPGA designs (most commonly targeted at Spartan-6, Virtex-4/5/6, and older families), RLOC is applied to primitives such as flip-flops, LUTs, and carry-chain elements that must maintain a fixed spatial relationship to each other; note that not every primitive type is placed independently in the same way, and RLOC is most naturally applied at the slice level within an RPM. The constraint uses a coordinate pair in the form `RLOC = X#Y#`, where the numbers are relative offsets within a group called an HGroup or VGroup, though the exact syntax and interpretation vary by device family and tool version. All elements sharing an RLOC group are placed together as a unit, with their internal arrangement locked, but the group's absolute anchor position is left to the place-and-route tools.

A common use case is constraining a carry-chain arithmetic block or a shift-register pipeline so that the elements land in adjacent slices and avoid routing detours. Timing-critical paths, such as fast adders or counters, benefit significantly because the placer cannot scatter the elements across the fabric when RLOC is applied. The blog post "Inside the Spartan-6: Using LUTs to optimize circuits" illustrates the kind of fine-grained slice-level awareness needed to use such constraints effectively.

One practical pitfall is over-constraining a design. Applying RLOC to too many elements reduces placer freedom, which can cause the tools to fail to fit the design or to produce worse timing on other paths. The constraint should be reserved for structures where the physical arrangement genuinely drives a timing or functional requirement, such as matched-length paths, RPMs (Relationally Placed Macros), or high-speed arithmetic trees.

RLOC constraints are typically written in a UCF (User Constraints File) for older Xilinx ISE flows; any use in XDC/Tcl under Vivado is limited and considered legacy rather than a standard modern workflow. Vivado has largely replaced RPM-style relative placement with Pblocks for most placement control, though Pblocks serve a somewhat different purpose and are not a direct equivalent. Awareness of the underlying slice geometry, including how LUTs, flip-flops, and carry logic share a slice, is necessary to write valid relative coordinates.

Frequently asked

What is the difference between RLOC and LOC constraints?
LOC pins a single element to a specific absolute fabric coordinate (e.g., SLICE_X4Y12). RLOC specifies a position relative to other elements within the same group, so the group can land anywhere the placer chooses while the internal arrangement is preserved. LOC is useful when you know exactly where something must go; RLOC is useful when you care about topology but not absolute position.
What is an RPM, and how does it relate to RLOC?
An RPM (Relationally Placed Macro) is a set of logic elements tied together with RLOC constraints and optionally an HGroup or VGroup attribute. RLOC is the per-element constraint; RPM is the collective term for the resulting group. The placer treats the RPM as a single movable block with a fixed internal layout.
Do RLOC constraints work in Vivado and on UltraScale devices?
Xilinx deprecated RLOC in the Vivado/UltraScale flow. Vivado uses Pblocks (physical blocks with absolute or relative regions) for placement guidance instead. RLOC remains relevant for designs targeting older families (Spartan-6, Virtex-6, and earlier) using ISE.
Can RLOC constraints cause a design to fail placement?
Yes. If the relative coordinates imply a shape that cannot fit within the available fabric at any location, or if too many RLOC groups reduce placer flexibility below what is needed to meet timing, the tools may report placement failures or produce a suboptimal result. Constraining only the truly timing-critical structures is recommended.
How do I determine valid RLOC coordinate values?
Coordinates are in slice units (X and Y offsets). You need to know the slice grid of the target device and how the logic elements you are grouping map onto slices. For carry-chain structures, elements must follow the vertical carry chain direction, so Y offsets must be monotonically increasing. Consulting the device architecture guide for the specific FPGA family (e.g., the Spartan-6 Libraries Guide) is necessary to avoid invalid placements.

Differentiators vs similar concepts

RLOC vs. LOC: LOC assigns an absolute fabric coordinate to a single element; RLOC assigns a coordinate relative to other elements in the same group (RPM). RLOC vs. Pblock (Vivado): A Pblock defines a rectangular region of the fabric and guides placement of a hierarchical cell into that region; it does not lock internal topology the way RLOC does, and the two mechanisms serve related but distinct purposes. Pblocks are the preferred mechanism in Vivado and on UltraScale/UltraScale+ devices, where RLOC is not supported.
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