SDRAM (Synchronous DRAM) is a type of dynamic RAM that synchronizes its command and data transfers to an external clock signal, allowing the memory controller to pipeline read and write transactions and sustain higher throughput than asynchronous DRAM. Unlike SRAM, SDRAM stores each bit in a capacitor cell that must be periodically refreshed to retain data.
In practice
SDRAM appears in embedded designs when the on-chip SRAM of a microcontroller or SoC is insufficient for the application, typically for frame buffers, audio sample buffers, large lookup tables, or general heap in Linux-capable systems. Common interfaces include single-data-rate SDR-SDRAM (running at 66-133 MHz) as well as DDR SDRAM variants such as LPDDR4/LPDDR5 on high-end application processors; these represent distinct interface families, not a single continuous range. MCU-class parts such as the STM32H7, i.MX RT1060, and NXP LPC546xx include dedicated external memory controller peripherals (variously named FMC, SEMC, or EMC depending on the family) that can interface SDRAM chips, though supported bus widths and SDRAM subtypes vary by subfamily and package.
Working with SDRAM requires correct initialization sequencing: the device must receive a power-up delay, a precharge-all command, a set number of auto-refresh cycles, and a mode-register write before normal operation. Getting this sequence wrong, or misconfiguring CAS latency, RAS-to-CAS delay (tRCD), or refresh interval (tREFI), is a common source of hard-to-reproduce data corruption. Many vendors supply a configuration wizard (STM32CubeMX, for example) that generates the register values, but validating those values against the SDRAM datasheet is still the developer's responsibility.
Refresh is the most operationally disruptive aspect of SDRAM in real-time systems. The memory controller must periodically issue auto-refresh commands (a common JEDEC guideline for many SDR/DDR parts is an average interval of 7.8 us at up to 85 degrees C, but the actual requirement depends on the specific device and density), during which the bus is unavailable. On latency-sensitive applications such as motor control or audio DSP, the firmware must account for worst-case refresh stalls when budgeting interrupt response time or DMA buffer sizes.
SDRAM is also a common component in FPGA-based embedded designs, where the developer must implement or instantiate a memory controller in fabric. Simulation of the controller against a SDRAM behavioral model before hardware bringup saves significant debug time; many FPGA toolchains supply IP blocks for common DDR SDRAM variants, but understanding the underlying protocol is essential for debugging timing failures or integrating non-standard devices.
Frequently asked
Why does SDRAM need refresh, and what happens if refresh is missed?
SDRAM stores each bit as charge on a small capacitor (a characteristic shared across SDR,
DDR, and LPDDR variants). Leakage current causes that charge to dissipate in milliseconds. Periodic refresh cycles (auto-refresh or self-refresh commands) re-read and rewrite each row before the charge falls below the sensing threshold. Missing refresh cycles causes data corruption that is often non-deterministic and temperature-dependent, since leakage increases with temperature. Many datasheets specify a maximum average refresh interval of 7.8 us at up to 85 degrees C and 3.9 us above that, but the exact figures depend on the specific part and density.
What is CAS latency, and why does it matter?
CAS latency (CL) is the number of clock cycles between asserting a read command and receiving valid data on the data bus. Lower CAS latency reduces read latency, but the minimum achievable CL is constrained by the SDRAM die and the clock frequency. It must be programmed into the device's mode register during initialization and must match the value the
memory controller expects; a mismatch causes data to be sampled at the wrong time, producing silent data errors.
What is the difference between SDR-SDRAM, DDR SDRAM, and LPDDR?
SDR-SDRAM transfers one data word per clock edge (single data rate).
DDR SDRAM transfers on both the rising and falling edges, doubling peak bandwidth at the same clock frequency. LPDDR (Low Power DDR) is a DDR variant optimized for mobile and embedded use, with lower supply voltages (LPDDR4 uses 1.1 V vs DDR4's 1.2 V) and additional power-saving modes. MCU-class external memory controllers typically support SDR or LPDDR2/3; application processors (i.MX 8, Rockchip RK3399, Allwinner A64) commonly interface LPDDR3 or LPDDR4.
Can I use SDRAM with a microcontroller that has no dedicated FMC/SEMC peripheral?
In principle, yes, by bit-banging the address, data, and command signals from GPIO, but the
timing constraints of SDRAM (nanosecond-scale setup/hold, strict refresh scheduling) make this impractical at useful speeds. Some designers use
SPI PSRAM (pseudo-static RAM with a serial interface, such as the ESP-PSRAM64H) as an easier alternative for MCUs without a parallel memory bus, accepting lower bandwidth in exchange for a simpler interface.
How do I handle SDRAM initialization in firmware?
The initialization sequence is device-specific but generally follows: (1) apply stable power and clock, then wait the required power-up delay (typically 100-200 us); (2) issue a Precharge All command; (3) issue the required number of Auto-Refresh commands (often 2 or 8, per the datasheet); (4) write the Mode Register to configure CAS latency, burst length, and burst type. After that, the device is ready for normal read/write access. Many MCU HAL libraries (STM32 HAL, NXP SDK) provide helper functions for this sequence, but you should verify each parameter against the SDRAM part's datasheet.
Differentiators vs similar concepts
SDRAM is often confused with SRAM: SRAM uses
flip-flop cells that retain state without refresh and offer lower latency and simpler interfacing, but are much larger in die area and cost more per bit. SDRAM is also distinct from PSRAM (pseudo-SRAM), which uses a DRAM cell array internally but presents a simple asynchronous or
SPI interface by handling refresh internally, hiding protocol complexity at the cost of bandwidth. Within the SDRAM family, SDR vs
DDR vs LPDDR are sometimes conflated: the key distinction is data rate per clock edge and supply voltage, not the fundamental DRAM operation, which is identical across all variants.
