A slice is the basic repeating logic unit inside the configurable logic blocks (CLBs) of Xilinx FPGAs, containing a fixed bundle of look-up tables (LUTs), flip-flops, carry-chain logic, and multiplexers that can be configured to implement combinational logic, registered logic, small distributed RAM, or shift registers. Slice count is a standard measure of resource utilization on Xilinx devices; other vendors use analogous but differently named structures (Altera/Intel calls theirs Adaptive Logic Modules or Logic Elements).
In practice
In most Xilinx 7-series and UltraScale devices, each slice typically contains four 6-input LUTs and eight flip-flops, along with dedicated carry logic, though exact contents vary by device family and slice type. 7-series has SLICEL (logic only) and SLICEM (logic plus distributed RAM/SRL) variants. UltraScale reorganizes the hierarchy slightly, but the slice remains the atomic unit reported by Vivado in utilization reports.
Slice count is the first number most developers check after synthesis and implementation. A design that fits comfortably in simulation may fail to place-and-route if slices are oversubscribed, or if the required slice types (SLICEM vs. SLICEL) are not available in sufficient quantity in the target part. The blog post "VGA Output in 7 Slices. Really." illustrates how aggressively a small design can be hand-optimized to minimize slice usage, a useful exercise for understanding what the tools are doing.
Because LUTs inside a slice can be repurposed as distributed SRAMs or shift registers (SRLs), with exact depths depending on LUT type and configuration mode, slices are not a flat resource. A design consuming many SLICEMs for distributed RAM leaves fewer available for general logic in that same tile region, which can create local routing congestion even when the global utilization percentage looks low. Always examine the per-region or per-SLR breakdown in large designs, not just the top-level percentage.
When choosing an FPGA for a new project, slice count (and type mix) is one of the primary sizing parameters alongside block RAM, DSP slices, and I/O count. The blog post "Choosing an Implementation Approach" and "Introduction to FPGA Technology" both discuss how to think about logic capacity when selecting a part or estimating whether a design will fit.
Learn this in FPGA Fundamentals
Discussed on FPGARelated
Frequently asked
How does a Xilinx slice relate to a CLB?
In 7-series devices, each
CLB contains two slices. The CLB is the placeable tile on the fabric grid; the slice is the functional subdivision within it.
Vivado utilization reports typically show both CLB and slice counts. UltraScale and UltraScale+ use a broadly similar structure, though the exact CLB-to-slice organization varies by family.
What is the difference between SLICEL and SLICEM?
On Xilinx 7-series FPGAs, SLICEM slices can configure their
LUTs as
distributed RAM or shift registers (SRLs) in addition to normal
combinational logic. SLICEL slices support only combinational and registered logic. The proportion of SLICEMs varies by device and part; heavy use of distributed RAM can exhaust SLICEMs locally even when overall utilization is modest.
Do Intel/Altera FPGAs have slices?
No. Intel/Altera uses different terminology: Cyclone and Arria families report Logic Elements (LEs) or Adaptive Logic Modules (ALMs). ALMs, used in families such as Stratix and Arria 10, are larger and more flexible than a simple
LUT-
FF pair, combining multiple LUT functions and registers in a single module, though the exact feature set is family-specific. The concepts are analogous but the structure, LUT size, and register count differ, so slice counts from Xilinx tools cannot be directly compared to ALM counts from Quartus.
Why can a design fail to fit even when slice utilization shows less than 100%?
Placement and routing are constrained by the physical grid. If a critical path or high-connectivity cluster needs resources in a specific region, that area can become a local bottleneck even though the global average looks fine. SLICEM exhaustion in a particular column, clock-region crossings, and routing congestion in dense areas are common causes.
Vivado's floorplanning and congestion views help identify these hotspots.
Is slice count a reliable way to compare logic complexity across different FPGA families?
Only roughly. Even within Xilinx, a 7-series slice (four 6-input
LUTs, eight FFs) differs in capability from a Spartan-6 slice (four 6-input LUTs, eight FFs but different carry and mux structure) or an older Virtex-4 slice (two 4-input LUTs, two FFs). Cross-vendor comparisons are even less reliable. Treat slice count as a same-family, same-tool utilization metric rather than an absolute measure of design complexity.
Differentiators vs similar concepts
A slice is specific to Xilinx
FPGA architecture. Intel/Altera FPGAs use Logic Elements (LEs) on older Cyclone/MAX families and Adaptive Logic Modules (ALMs) on Cyclone V, Arria, and Stratix families. Lattice iCE40 devices use Logic Cells (LCs), each with a single 4-input
LUT and one
flip-flop. Microsemi/Microchip PolarFire uses 4-input LUT4 cells. These are structurally different: an ALM is larger and more flexible than a 7-series SLICEL, while an iCE40 LC is smaller. Slice counts from Xilinx tools should never be used to estimate resource usage on a non-Xilinx device.
