SystemC is a C++ class library and IEEE standard (IEEE 1666) that adds hardware-description constructs — modules, ports, signals, and a discrete-event simulation kernel — to standard C++, enabling hardware/software co-design and transaction-level modeling (TLM) of digital systems.
In practice
SystemC is most commonly used at the architectural and transaction level rather than for RTL gate-level work. Designers build abstract models of SoCs — buses, processors, memory controllers, accelerators — where each component is a C++ class derived from sc_module. The simulation kernel handles concurrency through coroutine-style processes (SC_THREAD, SC_METHOD) and a delta-cycle mechanism, so multiple processes can communicate through sc_signal channels without explicit thread synchronization in user code.
In embedded system development, SystemC virtual platforms are frequently used to model a target SoC before silicon is available, allowing firmware and driver teams to start development and testing months earlier. The TLM-2.0 layer (part of IEEE 1666-2011) defines standard blocking and non-blocking transport interfaces for bus-level communication; many commercially available virtual platforms — such as those built with Synopsys Platform Architect or Arm Fast Models — expose TLM-2.0 sockets so that custom peripheral models can be plugged in alongside vendor-supplied IP, though not all platforms implement the standard interfaces in the same way.
At RTL, SystemC can be used to describe hardware using sc_logic, sc_bv, and clocked processes, and some EDA flows accept synthesizable SystemC alongside VHDL and Verilog; however, synthesizability depends on the specific tool and on adhering to a restricted subset of constructs — not every use of those types or clocked processes is guaranteed to be synthesizable. In practice, most teams reserve VHDL or Verilog/SystemVerilog for RTL and use SystemC specifically where the behavioral abstraction or tight C++ integration is valuable — for example, a fixed-point DSP algorithm validated in C++ can be wrapped in an sc_module with minimal friction.
A common pitfall is underestimating the simulation performance cost of fine-grained modeling. Because every signal assignment may trigger delta cycles, a large SystemC model with excessive signal granularity can run orders of magnitude slower than a loosely timed TLM model. Teams new to SystemC often start at too low an abstraction level and discover this only when simulation throughput becomes impractical for running meaningful software workloads.
Frequently asked
How does SystemC differ from VHDL or Verilog?
VHDL and
Verilog are purpose-built HDLs with syntax designed around hardware concurrency and are widely used input languages for
synthesis and formal tools, alongside
SystemVerilog and other
RTL subsets. SystemC is a C++ library, so models compile with any standard C++ compiler and integrate directly with other C++ code — test benches, firmware, algorithm models. This makes SystemC more flexible for system-level and behavioral work, but most RTL synthesis flows still expect VHDL or Verilog rather than SystemC.
What is TLM-2.0 and why does it matter for embedded developers?
TLM-2.0 (Transaction-Level Modeling 2.0) is a standard API within IEEE 1666 for modeling bus transactions as function calls rather than as cycle-by-cycle signal toggles. An initiator calls a transport function on a target socket, passing a generic payload (address, data, command). This abstraction runs much faster in
simulation than
RTL signal-level models, making it practical to boot a real OS image or run a full firmware test suite on a virtual platform long before hardware is available.
Can SystemC be used for synthesis?
A synthesizable subset of SystemC exists and some tools — including Cadence Stratus and Mentor Catapult — accept it for
high-level synthesis (HLS). The synthesizable subset restricts constructs to clocked SC_METHOD processes and fixed-width types such as sc_int and sc_uint. Arbitrary C++ features like dynamic allocation and virtual functions are not synthesizable. For most projects,
VHDL or
Verilog remains the
RTL handoff format even when SystemC is used upstream.
Do I need a special simulator to run SystemC models?
No. Because SystemC is a C++ library, a model compiles and links like any C++ program. The open-source reference implementation from Accellera compiles with GCC, Clang, or MSVC. Commercial simulators such as QuestaSim and VCS also have native SystemC support and can co-simulate SystemC modules alongside
VHDL and
Verilog. This is unlike VHDL, which requires a dedicated
simulator such as GHDL (discussed in the EmbeddedRelated post 'Using GHDL for interactive simulation under Linux') or a commercial tool.
What is the difference between sc_signal and a regular C++ variable for communicating between processes?
sc_signal implements the SystemC request-update protocol: a write during a time step is buffered and only becomes visible to readers after a delta cycle. This ensures that all processes reading the signal in the current delta see the old value, matching the semantics of hardware signals and preventing order-of-evaluation artifacts. A plain C++ variable has no such protection and would cause non-deterministic results if two concurrent SC_METHOD processes both read and write it in the same
simulation step.
Differentiators vs similar concepts
SystemC is often compared to
VHDL and
Verilog. The key distinction is abstraction level and host language integration: VHDL and Verilog are standalone HDLs primarily targeting
RTL and gate-level
simulation and
synthesis; SystemC is a C++ library that targets system-level and transaction-level modeling and integrates natively with C/C++ firmware, drivers, and algorithm code. SystemC is also sometimes confused with
HLS tools like Xilinx Vitis HLS or Catapult, which accept a C/C++ subset as input; those tools generate RTL automatically, whereas SystemC itself is a simulation and modeling framework and does not generate RTL unless used within an HLS tool that explicitly supports it.
