Vivado is Xilinx's (now AMD's) integrated design environment for FPGA and SoC development, targeting 7-series and newer device families (Artix, Kintex, Virtex, Zynq, UltraScale, UltraScale+). It covers the full design flow from RTL entry and IP integration through synthesis, implementation, bitstream generation, and hardware debugging.
In practice
Vivado is the standard toolchain for all Xilinx devices from the 7-series onward, superseding the older ISE toolchain for those families (ISE remains the tool for pre-7-series parts). Designers write RTL in VHDL or Verilog (or SystemVerilog), then drive synthesis and place-and-route through either the Vivado GUI or Tcl scripts. Tcl scripting is particularly important for reproducible, CI-friendly builds; most serious projects store a project-reconstruction script in version control rather than committing the full Vivado project directory.
The IP Integrator (IPI) block-diagram canvas is the standard way to assemble Zynq and MicroBlaze-based SoC designs, wiring together Xilinx IP cores, AXI interconnect, and custom RTL blocks. Projects connecting FPGA fabric to a host over PCIe, for example the kind of framework described in "Introducing the VPCIe framework," are typically assembled this way, relying on Vivado's AXI and PCIe IP cores as a foundation.
Vivado includes the Vivado Logic Analyzer (formerly ChipScope), which inserts ILA (Integrated Logic Analyzer) cores into the fabric to capture internal signals at runtime without requiring additional on-chip debug hardware beyond the ILA core itself. A JTAG connection and a host running Vivado Hardware Manager are still needed. This is often the fastest path to debugging timing-sensitive or intermittent logic bugs that cannot be observed through external pins alone.
Vivado also supports C/C++ high-level synthesis through Vitis HLS (formerly Vivado HLS), which allows designers to describe hardware in C and compile it to RTL. The relationship between Vitis HLS and Vivado has shifted across tool versions; in current flows it is typically a separate tool whose output is imported into Vivado as an IP core rather than being deeply integrated within Vivado itself. In practice, the quality of results varies significantly with coding style and the nature of the algorithm; as discussed in "Little to no benefit from C based HLS," HLS is not a universal productivity win and hand-written RTL often produces better or more predictable results for many common embedded workloads.
Discussed on FPGARelated
Frequently asked
Which Xilinx device families does Vivado support?
Vivado supports 7-series (Artix-7, Kintex-7, Virtex-7, Zynq-7000) and all subsequent families: UltraScale, UltraScale+, Versal, and the associated Zynq UltraScale+ MPSoC and RFSoC parts. Older families (Spartan-6, Virtex-6, and earlier) are supported only by the legacy
ISE toolchain, not Vivado.
Do I need a license to use Vivado?
AMD offers a free Vivado ML Standard edition that supports smaller devices, including certain Artix-7 parts commonly found on popular development boards. Larger devices and advanced features such as
partial reconfiguration require a paid license or a device-locked node-locked license. The exact device and edition matrix is version-dependent and has changed across Vivado releases, so check the current AMD licensing page for up-to-date details.
What is the difference between Vivado and Vitis?
Vivado handles the hardware side:
RTL design, IP integration,
synthesis, implementation, and
bitstream generation. Vitis is the software development environment layered on top, used for writing and debugging C/C++ applications that run on the ARM cores in Zynq or
MicroBlaze soft processors. For pure
FPGA fabric designs with no embedded processor software, Vivado alone is typically sufficient.
How do I use a soft-core processor like MicroBlaze or PicoBlaze inside a Vivado project?
MicroBlaze is instantiated through IP Integrator as an
AXI-based subsystem; Vivado generates the hardware handoff files consumed by Vitis for software development. PicoBlaze is a much smaller soft-core typically delivered as a macro or core with associated support files, and it is instantiated at the
RTL level rather than through IP Integrator, though it should not be treated as identical to a plain user-authored RTL module. The blog post 'PicoBlaze - Program RAM Access for an Interactive Monitor' covers one technique for making PicoBlaze firmware more interactive within this flow.
Can I use Vivado with open-source or alternative HDL workflows?
Vivado's
synthesis and implementation engines are closed, but Vivado can be driven entirely via Tcl, which makes it possible to integrate with open-source tooling. Some workflows use only Vivado for place-and-route while generating
RTL from tools like MyHDL or Amaranth. Full open-source alternatives (e.g., Yosys plus nextpnr) exist for subsets of Xilinx 7-series parts, but support is partial and in some cases experimental, with coverage varying by specific device; support for UltraScale or newer families is not available in these flows.
Differentiators vs similar concepts
Vivado is often compared to
Xilinx ISE and to Intel/Altera Quartus Prime. ISE is the predecessor toolchain for pre-7-series Xilinx devices; it is no longer actively developed and does not support 7-series or newer parts. Quartus Prime is Intel's equivalent environment for Cyclone, Arria, and Stratix FPGAs; it shares a similar design flow (
RTL entry, IP catalog, place-and-route, SignalTap logic analyzer) but targets entirely different silicon and uses a different constraint format and Tcl dialect. Vivado should also be distinguished from Vitis: Vivado owns the hardware design and
bitstream, while Vitis owns the embedded software built on top of it.
