Wishbone is an open, royalty-free on-chip interconnect specification originally developed by Silicore Corporation and now maintained by the OpenCores community. It defines a simple synchronous bus interface, including signal naming, timing, and handshaking rules, intended to allow IP cores from different designers to be connected without glue logic.
In practice
Wishbone is most commonly encountered in the OpenCores and open-source FPGA ecosystem. Soft-core processors such as the OpenRISC 1000, ZipCPU, and the J1 Forth CPU (discussed in "Homebrew CPUs: Messing around with a J1") use Wishbone as their primary bus, and peripheral IP cores for UART, SPI, I2C, and memory controllers written for those ecosystems typically expose a Wishbone slave interface. When assembling an SoC on an FPGA, Wishbone lets you connect a soft CPU to multiple peripherals through a shared bus or a crossbar interconnect with minimal adapter logic, provided all cores conform to the same revision of the spec.
The core handshake uses a small set of signals: CLK_I (clock), RST_I (reset), ADR_I (address), DAT_I/DAT_O (data), WE_I (write enable), STB_I (strobe, indicating a valid cycle), CYC_I (bus cycle active), ACK_O (acknowledgment from slave), and optionally ERR_O and RTY_O. A transaction completes when both STB_I and ACK_O are asserted in the same clock cycle in the common synchronous handshake, though exact timing interpretation depends on the cycle type and variant in use. This makes the protocol straightforward to implement in HDL, and a slave can insert wait states simply by delaying ACK_O.
Wishbone defines several bus topologies: point-to-point, shared bus, and crossbar switch. Intercon logic (the bus fabric) is typically generated or written by hand for each SoC configuration. Because the spec allows wide latitude in optional signals and cycle types (classic, registered feedback, block transfer, and burst), interoperability between cores from different sources requires checking that both sides implement the same subset. Mismatched cycle types or incorrect handling of CYC_I vs. STB_I are common integration bugs.
The most commonly referenced revisions in practice are B3 and B4, though older revision variants and compatibility subsets remain present in the ecosystem. Revision B4 is associated with pipelined transfers, which allow a master to issue new addresses before receiving ACKs for prior transactions, significantly improving throughput to high-latency peripherals such as SDRAM controllers; in practice, some designs use subsets or mixed interpretations of pipelined behavior across revisions. Designers connecting cores from different sources should verify which revision each core targets, as B4 pipelined slaves are not directly compatible with B3 masters without an adapter.
Frequently asked
Is Wishbone specific to FPGAs, or can it be used in ASICs?
Wishbone is silicon-agnostic; the specification describes logical signal behavior and timing, not a physical implementation. It has been used in both
FPGA-based SoC designs and in taped-out ASICs, particularly in the OpenCores and LibreCores communities. In practice, most hobbyist and open-source usage is on FPGAs.
How does Wishbone compare to AXI-Lite for connecting peripherals to a soft CPU?
Both target on-chip peripheral interconnect.
AXI-Lite (part of ARM's AMBA spec) is more widely supported by commercial EDA tools, vendor IP wizards (Xilinx/AMD Block Design, Intel Platform Designer), and hard ARM cores. Wishbone is simpler to implement by hand, is fully open and royalty-free, and is the dominant bus in the OpenCores IP library. If you are integrating third-party commercial IP or using a vendor's hard ARM subsystem, AXI-Lite is more practical. If you are building a fully open-source
FPGA SoC around a soft CPU, Wishbone is a natural fit.
What is the difference between Wishbone B3 and B4?
Revision B3 defines classic single-read/write cycles and basic block transfers, where a new address can only be issued after the current ACK is received. Revision B4 is associated with a pipelined cycle type in which the master can present a new address on every clock cycle without waiting for the previous ACK, allowing the slave to return acknowledgments with a fixed or variable latency. B4 pipelined mode significantly increases throughput to memory controllers and other high-latency peripherals, though some designs implement subsets or mixed interpretations of pipelined behavior.
What does STB_I signal, and why is it separate from CYC_I?
CYC_I indicates that the master holds the bus and the overall bus cycle is active. STB_I qualifies a specific data transfer request within that cycle. The separation allows a master to hold the bus across multiple transfers (keeping CYC_I asserted) while momentarily deasserting STB_I between individual strobe events, such as during burst transfers where the master needs a cycle to prepare the next address. In general, a compliant slave responds to a transfer when both CYC_I and STB_I are asserted, though the exact behavior can depend on cycle type and registered or pipelined variants.
Where can I find Wishbone IP cores to use in a project?
OpenCores (opencores.org) hosts a large library of Wishbone-compatible IP, including UART,
SPI, I2C, Ethernet MAC, and memory controllers. The LibreCores project and various GitHub repositories (ZipCPU/wb2axip, for example) also provide well-documented Wishbone cores and interconnect utilities. Always confirm which Wishbone revision a core targets before integration.
Differentiators vs similar concepts
Wishbone is often compared to AMBA
AXI/AXI-Lite and Avalon (Intel/Altera). AXI and Avalon are vendor-backed standards with strong EDA tool integration and are required for connecting to hard IP blocks (ARM hard cores, vendor memory controllers). Wishbone is fully open and royalty-free, simpler to implement by hand, and dominant in the OpenCores IP ecosystem, but lacks the tooling support of AXI. Within the AMBA family, AXI-Lite is the closest functional analog to Wishbone classic cycles: both are simple synchronous request/acknowledge interfaces targeting low-bandwidth control-register-style peripherals. AXI4 full (with bursting and out-of-order transactions) has no direct Wishbone equivalent, though Wishbone B4 pipelined mode partially addresses throughput with in-order pipelining.
