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What happened to the OpenCores website

Started by Wojciech Zabolotny in comp.arch.fpga1 year ago 3 replies

I have noticed, that the categories on the list of projects https://opencores.org/projects do not unfold after clicking. That makes browsing...

I have noticed, that the categories on the list of projects https://opencores.org/projects do not unfold after clicking. That makes browsing projects impossible. Is it a problem with my browser (Firefox on Linux) or with the website? Regards, Wojtek


Excess 3 Adder: Add 2 three digits numbers in excess 3.

Started by Virulog_X in comp.arch.fpga1 year ago 2 replies

Excess 3 Adder: Add 2 three digits numbers in excess 3. ex. 998+345 in excess 3. i don't have any idea on how to continue, please help. thx...

Excess 3 Adder: Add 2 three digits numbers in excess 3. ex. 998+345 in excess 3. i don't have any idea on how to continue, please help. thx ! module Decimal_to_E3(input[10:0] dec, output reg[15:0] E3); reg[10:0] aux; reg[1:0] counter; always @ (dec) begin aux = dec; E3 = {4{4'b0011}}; counter = 2'b00; while(aux != 0) begin E3[counter * 4 +: 4] = aux % 10 + 3; aux = aux / 10; coun...


Program Counter in Verilog. Case not working.

Started by SpainHack in comp.arch.fpga1 year ago 5 replies

Hello All,=20 I'm just getting started with Verilog.=20 I created the following Programs Counter for a simple Stack Machine.=20 The PC is an...

Hello All,=20 I'm just getting started with Verilog.=20 I created the following Programs Counter for a simple Stack Machine.=20 The PC is an 8-bit register that stores the address of the command being e= xecuted. The clock pulse at the positive edge of the clock signal (except mode =3D 2= ). If mode =3D 0 reset PC to 0 If mode =3D 1, set the PC value to be equal to the value in the data...


Disabled generate gives compile error in Modelsim

Started by Stef in comp.arch.fpga1 year ago 1 reply

[This is a repost. Posted this to comp.lang.vhdl a few days ago, but no replies. So maybe nobody knows the answer, it was a malformed...

[This is a repost. Posted this to comp.lang.vhdl a few days ago, but no replies. So maybe nobody knows the answer, it was a malformed question or there are no readers in that group. So a repost (with a little clarification, I hope) with the comp.arch.fpga added at least resolves the last option. ;-)] It has been a while since I used VHDL so I am a little rusty. Did not much use the gener...


Trion bitstream compression test

Started by John Larkin in comp.arch.fpga1 year ago 4 replies

Suppose we read in an FPGA bitstream file as 16-bit words, and want to output a compressed file, to save room in a small flash chip. If an...

Suppose we read in an FPGA bitstream file as 16-bit words, and want to output a compressed file, to save room in a small flash chip. If an input word is 0000, output a single 0 bit to the compressed file. If a word is nonzero, output a 1 followed by that 16-bit word. The decompressor will be very simple. I wrote a little PowerBasic program to test the compression, the input being ...


Where can I find solutions to my problems?

Started by JAMMY Anderson in comp.arch.fpga1 year ago

https://t.co/4xQ8CXBhmm

https://t.co/4xQ8CXBhmm


efinix bit stream question

Started by John Larkin in comp.arch.fpga1 year ago 10 replies

We use the efinix T20 trion FPGA. Questions about the config bit streams: Are they always the same size, or does it depend on how much logic...

We use the efinix T20 trion FPGA. Questions about the config bit streams: Are they always the same size, or does it depend on how much logic is compiled? Would a simple application use less? Are the streams very compressible? We have done some simple run-length coding to greatly reduce the storage requirement for other FPGAs. Configs tend to have long runs of 0's. The T20/256 claims...


Developing older Xilinx FPGA and CPLD XC3S500E

Started by Cy Drollinger in comp.arch.fpga1 year ago 2 replies

I have some old chips and in light of the shortages I continually see despi= te the 52 week lead time thrown around in the summer of 2020, I...

I have some old chips and in light of the shortages I continually see despi= te the 52 week lead time thrown around in the summer of 2020, I would like = to develop with them. Specifically, I am talking about Spartan 3E parts and= would like to know about setting up a stable toolchain with Win10 or 11. T= his could include Ubunutu 20.04 on WSL2. Does anyone have a decent recipe t= o develop ...


How to change the font size in text editor of modelsim

Started by fl in comp.arch.fpga1 year ago 2 replies

Hi, I am using Modelsim 6.2e with the Xilinx webpack 8.2. When I print the vhdl text from the text editor of Modelsim, the font size is very...

Hi, I am using Modelsim 6.2e with the Xilinx webpack 8.2. When I print the vhdl text from the text editor of Modelsim, the font size is very big. How to modify the font size in the printed paper? I do not find such dialogue box. Thank you very much.


Forcing Synopsys to use only DFFs

Started by Chris Johnson in comp.arch.fpga1 year ago 1 reply

I have an application that needs to assure that the FFs reloaded from the combinatorial logic at their inputs on every clock in order to flush...

I have an application that needs to assure that the FFs reloaded from the combinatorial logic at their inputs on every clock in order to flush radiation induced errors with TMR corrected values. The FPGA that I am using can implement enable FFs or D FFs. Is it possible to force Synopsys to not use only D FFs to assure that the stored values are updated on every clock? -Chris


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