https://fpgaer.tech/?p=561

https://fpgaer.tech/?p=561

My customer is asking for a redesign of a very profitable board to deal with components that are EOL. Because of delivery issues from the EOL...

My customer is asking for a redesign of a very profitable board to deal with components that are EOL. Because of delivery issues from the EOL components, they are asking for the IP and manufacturing rights if I can't build them adequately. This seems a bit egregious, but I'm willing to do it if I can protect my financial interests. The ideal solution would be a device of some

Research Assistantship at the Graduate School, Dept. of Computer Engineering, Hallym University, Korea The [AI Accelerator Design Lab] of the...

Research Assistantship at the Graduate School, Dept. of Computer Engineering, Hallym University, Korea The [AI Accelerator Design Lab] of the Hallym University seek to recruit promising PhD and MSc or MSc-PhD research students. The selected students will conduct research in the [Edge Computing for Deep Learning Algorithms]. Interested applicants should contact Prof. Lee, Jeong-Gun

Magellan HW monitor for Basys 3 board - Access register banks for reading/writing via JTAG to AXI adapter. Can also monitor register values via...

Magellan HW monitor for Basys 3 board - Access register banks for reading/writing via JTAG to AXI adapter. Can also monitor register values via the board seven-segment display (register address is selected through SW0-3) https://fpgaer.tech/?p=465

To generate frequencies from approximately 0.5 mHz to 12 MHz with a DDS a minimum clock of > 24, say 25 MHz, is required. To be able to go...

To generate frequencies from approximately 0.5 mHz to 12 MHz with a DDS a minimum clock of > 24, say 25 MHz, is required. To be able to go down to 0.5 mHz, a phase accumulator of at least 36 bits is required. This will give sub mHz resolution over the entire range. Nice for the low frequencies, but not of much use for MHz frequencies (in this application). Is there any objection to using a

Anyone using Efinix parts? They look ok, even if they don't have a lot of package offerings. The smallest part has a 0.5A surge at power on. ...

Anyone using Efinix parts? They look ok, even if they don't have a lot of package offerings. The smallest part has a 0.5A surge at power on. The list it as "minimum", I'm guessing they mean the minimum required by the supply. They also don't provide software until you buy an eval board, so no way to check that out, up front. Funny company, but not as "funny" as Cologne Chip. They ...

Hello guys, I am student at high school interested in VHDL programming and = post quantum algorithms. I have a code where algorithm is divided to...

Hello guys, I am student at high school interested in VHDL programming and = post quantum algorithms. I have a code where algorithm is divided to three = parts. Each part is a component. I would like to create another component, = which will put input to one of those three components, this component will = create output, this will be input to the third component and this one will = create fin...

Dear VHDL Coders, I am trying to get the rank of elements from an array of data. For example, I have an array, Voltage = [20 40 10 30] ; The...

Dear VHDL Coders, I am trying to get the rank of elements from an array of data. For example, I have an array, Voltage = [20 40 10 30] ; The position of the elements in the voltage array is ranged from 0 to 3. Using a bubble sorting algorithm, I obtained the position index of the elements in the array as follows: Index (0)= 2 ; Index (1)= 0 ; Index (2)= 3 ; Index (3)= 1 ; However, ba...

The 32-bit version should have better latency performance but I think it's more complex, so it should use more resources. But as the link...

The 32-bit version should have better latency performance but I think it's more complex, so it should use more resources. But as the link below https://www.xilinx.com/html_docs/ip_docs/pru_files/ten-gig-eth-pcs-pma.html 32-bit version is better in all kinds of aspects of resource utilization. If the 32-bit version has better latency, needs less resource. What's its cost to get these ...

For support of an old product, we may need to modify a Xilinx Spartan 3 FPGA. This was originally designed in VHDL with Modelsim Designer...

For support of an old product, we may need to modify a Xilinx Spartan 3 FPGA. This was originally designed in VHDL with Modelsim Designer and ISE 9.2, both no longer available. New Vivado versions do not seem to support Spartan 3. What are the current options for making changes to a Spartan 3 design? -- Stef Facts are stubborn, but statistics are more pliable.