FPGARelated.com

Renesas has a 1 kLUT FPGA!

Started by gnua...@gmail.com in comp.arch.fpga1 year ago 2 replies

I guess I've heard something about this before, but it must have bounced off and not sunk in. Here's the data sheet. SLG47910...

I guess I've heard something about this before, but it must have bounced off and not sunk in. Here's the data sheet. SLG47910 - https://community.renesas.com/cfs-file/__key/communityserver-discussions-components-files/293/SL G47910_5F00_ds_5F00_2v3.pdf I guess it's not ready for production as yet. -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https:/


Renesas GreenPAK Sales/FAE Support

Started by gnua...@gmail.com in comp.arch.fpga1 year ago

I've been considering a Greenpak device or two or even three, in a respin of a new design. I've identified three functions that the Greenpak...

I've been considering a Greenpak device or two or even three, in a respin of a new design. I've identified three functions that the Greenpak devices could replace on my board, but not all in the same part! LOL I'd like to discuss this design with an FAE or salesperson, but I can't seem to get any replies. The Renesas website was clearly created by pointy haired bosses in legi


Intel announces new FPGA families

Started by Claudio Avi Chami in comp.arch.fpga1 year ago 2 replies

https://fpgaer.tech/?p=561

https://fpgaer.tech/?p=561


Hardware based IP protection of FPGA designs

Started by gnua...@gmail.com in comp.arch.fpga1 year ago 10 replies

My customer is asking for a redesign of a very profitable board to deal with components that are EOL. Because of delivery issues from the EOL...

My customer is asking for a redesign of a very profitable board to deal with components that are EOL. Because of delivery issues from the EOL components, they are asking for the IP and manufacturing rights if I can't build them adequately. This seems a bit egregious, but I'm willing to do it if I can protect my financial interests. The ideal solution would be a device of some


Research Assistantship at the Graduate School, Dept. of Computer Engineering, Hallym University, Korea

Started by jg.lee in comp.arch.fpga2 years ago

Research Assistantship at the Graduate School, Dept. of Computer Engineering, Hallym University, Korea The [AI Accelerator Design Lab] of the...

Research Assistantship at the Graduate School, Dept. of Computer Engineering, Hallym University, Korea The [AI Accelerator Design Lab] of the Hallym University seek to recruit promising PhD and MSc or MSc-PhD research students. The selected students will conduct research in the [Edge Computing for Deep Learning Algorithms]. Interested applicants should contact Prof. Lee, Jeong-Gun


Magellan VHDL monitor for Basys 3 board

Started by Claudio Avi Chami in comp.arch.fpga2 years ago

Magellan HW monitor for Basys 3 board - Access register banks for reading/writing via JTAG to AXI adapter. Can also monitor register values via...

Magellan HW monitor for Basys 3 board - Access register banks for reading/writing via JTAG to AXI adapter. Can also monitor register values via the board seven-segment display (register address is selected through SW0-3) https://fpgaer.tech/?p=465


Last CFP: 22nd International Conference on Hybrid Intelligent Systems (HIS'22) - Online - Springer Publication

Started by Anu Bajaj in comp.arch.fpga2 years ago

* Final Call for Papers - please circulate this CFP to your colleagues and networks ** We are sending you an invitation for the 22nd...

* Final Call for Papers - please circulate this CFP to your colleagues and networks ** We are sending you an invitation for the 22nd International Conference on Hybrid Intelligent Systems (HIS'22) held during December 13-15, 2022. We are looking forward to receiving your research papers and seeing you online during ISDA 2022. A detailed call for papers is given below. We hope you wi


Wide frequency range, arbitrary waveform DDS

Started by Stef in comp.arch.fpga2 years ago 22 replies

To generate frequencies from approximately 0.5 mHz to 12 MHz with a DDS a minimum clock of > 24, say 25 MHz, is required. To be able to go...

To generate frequencies from approximately 0.5 mHz to 12 MHz with a DDS a minimum clock of > 24, say 25 MHz, is required. To be able to go down to 0.5 mHz, a phase accumulator of at least 36 bits is required. This will give sub mHz resolution over the entire range. Nice for the low frequencies, but not of much use for MHz frequencies (in this application). Is there any objection to using a


Efinix FPGA

Started by gnua...@gmail.com in comp.arch.fpga2 years ago 17 replies

Anyone using Efinix parts? They look ok, even if they don't have a lot of package offerings. The smallest part has a 0.5A surge at power on. ...

Anyone using Efinix parts? They look ok, even if they don't have a lot of package offerings. The smallest part has a 0.5A surge at power on. The list it as "minimum", I'm guessing they mean the minimum required by the supply. They also don't provide software until you buy an eval board, so no way to check that out, up front. Funny company, but not as "funny" as Cologne Chip. They ...


2nd CFP: 18th International Conference on Information Assurance and Security (IAS 2022) - Online - Springer Publication

Started by Dr.Aswathy SU in comp.arch.fpga2 years ago

** Second Call for Papers - please circulate this CFP to your colleagues and networks ** -- 18th International Conference on Information...

** Second Call for Papers - please circulate this CFP to your colleagues and networks ** -- 18th International Conference on Information Assurance and Security (IAS 2022) -- http://www.mirlabs.org/ias22 http://www.mirlabs.net/ias22 On the World Wide Web December 13-15,2022 ** Plenary Speakers ** ------------------------------ Catarina Silva, University of Coimbra, Por


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