Hello guys, I am student at high school interested in VHDL programming and = post quantum algorithms. I have a code where algorithm is divided to...

Hello guys, I am student at high school interested in VHDL programming and = post quantum algorithms. I have a code where algorithm is divided to three = parts. Each part is a component. I would like to create another component, = which will put input to one of those three components, this component will = create output, this will be input to the third component and this one will = create fin...

Dear VHDL Coders, I am trying to get the rank of elements from an array of data. For example, I have an array, Voltage = [20 40 10 30] ; The...

Dear VHDL Coders, I am trying to get the rank of elements from an array of data. For example, I have an array, Voltage = [20 40 10 30] ; The position of the elements in the voltage array is ranged from 0 to 3. Using a bubble sorting algorithm, I obtained the position index of the elements in the array as follows: Index (0)= 2 ; Index (1)= 0 ; Index (2)= 3 ; Index (3)= 1 ; However, ba...

The 32-bit version should have better latency performance but I think it's more complex, so it should use more resources. But as the link...

The 32-bit version should have better latency performance but I think it's more complex, so it should use more resources. But as the link below https://www.xilinx.com/html_docs/ip_docs/pru_files/ten-gig-eth-pcs-pma.html 32-bit version is better in all kinds of aspects of resource utilization. If the 32-bit version has better latency, needs less resource. What's its cost to get these ...

For support of an old product, we may need to modify a Xilinx Spartan 3 FPGA. This was originally designed in VHDL with Modelsim Designer...

For support of an old product, we may need to modify a Xilinx Spartan 3 FPGA. This was originally designed in VHDL with Modelsim Designer and ISE 9.2, both no longer available. New Vivado versions do not seem to support Spartan 3. What are the current options for making changes to a Spartan 3 design? -- Stef Facts are stubborn, but statistics are more pliable.

I am trying to understand the correct way to calculate throughput of a digital hardware design block that forms part of a bigger system. Here...

I am trying to understand the correct way to calculate throughput of a digital hardware design block that forms part of a bigger system. Here are the few scenarios: 1. DUT takes 10 clock cycles to generate 20 bit output, then another 10 clock cycles to generate the next 20 bit output. -> The maximum throughput is 20 bits per 10 clock cycles = 2 bits/cycle 2. DUT takes 10 clock cycles to ge

Hello, I have a Stratix 10 design that is based around an ip core generated using = Intel's HLS. The core does some simple floating point...

Hello, I have a Stratix 10 design that is based around an ip core generated using = Intel's HLS. The core does some simple floating point operations and by its= elf uses very few resources (1 DSP, a few hundred flops etc). This core sits inside a generate statement like this: generate for(i =3D 0; i < SOMEBIGNUMBER; i=3Di+1) myhlscore u0 (inputs, outputs); ... The de

I am in possession of a book that says if the gate of an N-channel MOSFET is low (say 0 volts), then the output is high impedance; and that if...

I am in possession of a book that says if the gate of an N-channel MOSFET is low (say 0 volts), then the output is high impedance; and that if that gate is high (say 5 volts), then the voltage at the drain depends on the voltage at the source; if the voltage at the source is low, then the voltage at the drain is low; but if the voltage at the source is high (say 5 volts), then the v

I found my old BeMicro Cyclone III board laying around the other day and happen to have a use for it - if I can get it running again. I know it's...

I found my old BeMicro Cyclone III board laying around the other day and happen to have a use for it - if I can get it running again. I know it's an ancient board, but this project doesn't need much, and this old device would be perfect. Unfortunately, none of my current machines are capable of running the drivers that came with it. They are all running either Windows 10 64-bit or 6

I don't know if this is the right forum to post this to. If there's a forum= that would be more appropriate for a question like this, please let...

I don't know if this is the right forum to post this to. If there's a forum= that would be more appropriate for a question like this, please let me kno= w. Let's say for a moment that I need to build a Random Access Memory that con= sists of 256 nybbles. An eight-bit address bus and a four-bit data bus conn= ect the CPU to each of the 256 nybbles. To make things simple, let's assume= tha...

Today I tried to find certain old post on the Xilinx forum. Goggle has found it in their database, but the link leads to nowhere and is finally...

Today I tried to find certain old post on the Xilinx forum. Goggle has found it in their database, but the link leads to nowhere and is finally redirected to https://support.xilinx.com/s/ . There is no forum available any more. Does it mean that all the knowledge created by the users is lost forever? If I remember it happened once in the past with Xilinx forum. Have they done it again? Reg...