I am trying to understand the correct way to calculate throughput of a digital hardware design block that forms part of a bigger system. Here...

I am trying to understand the correct way to calculate throughput of a digital hardware design block that forms part of a bigger system. Here are the few scenarios: 1. DUT takes 10 clock cycles to generate 20 bit output, then another 10 clock cycles to generate the next 20 bit output. -> The maximum throughput is 20 bits per 10 clock cycles = 2 bits/cycle 2. DUT takes 10 clock cycles to ge

Hello, I have a Stratix 10 design that is based around an ip core generated using = Intel's HLS. The core does some simple floating point...

Hello, I have a Stratix 10 design that is based around an ip core generated using = Intel's HLS. The core does some simple floating point operations and by its= elf uses very few resources (1 DSP, a few hundred flops etc). This core sits inside a generate statement like this: generate for(i =3D 0; i < SOMEBIGNUMBER; i=3Di+1) myhlscore u0 (inputs, outputs); ... The de

I am in possession of a book that says if the gate of an N-channel MOSFET is low (say 0 volts), then the output is high impedance; and that if...

I am in possession of a book that says if the gate of an N-channel MOSFET is low (say 0 volts), then the output is high impedance; and that if that gate is high (say 5 volts), then the voltage at the drain depends on the voltage at the source; if the voltage at the source is low, then the voltage at the drain is low; but if the voltage at the source is high (say 5 volts), then the v

I found my old BeMicro Cyclone III board laying around the other day and happen to have a use for it - if I can get it running again. I know it's...

I found my old BeMicro Cyclone III board laying around the other day and happen to have a use for it - if I can get it running again. I know it's an ancient board, but this project doesn't need much, and this old device would be perfect. Unfortunately, none of my current machines are capable of running the drivers that came with it. They are all running either Windows 10 64-bit or 6

I don't know if this is the right forum to post this to. If there's a forum= that would be more appropriate for a question like this, please let...

I don't know if this is the right forum to post this to. If there's a forum= that would be more appropriate for a question like this, please let me kno= w. Let's say for a moment that I need to build a Random Access Memory that con= sists of 256 nybbles. An eight-bit address bus and a four-bit data bus conn= ect the CPU to each of the 256 nybbles. To make things simple, let's assume= tha...

Today I tried to find certain old post on the Xilinx forum. Goggle has found it in their database, but the link leads to nowhere and is finally...

Today I tried to find certain old post on the Xilinx forum. Goggle has found it in their database, but the link leads to nowhere and is finally redirected to https://support.xilinx.com/s/ . There is no forum available any more. Does it mean that all the knowledge created by the users is lost forever? If I remember it happened once in the past with Xilinx forum. Have they done it again? Reg...

Hi all, I am trying to build a sequence detector to detect a decimal number like 10= 92 when a stream of numbers from 0-9 is given as input....

Hi all, I am trying to build a sequence detector to detect a decimal number like 10= 92 when a stream of numbers from 0-9 is given as input. Do you think just c= hanging the width of input i.e parallel inputs instead of series would resu= lt in pattern detection? I am lost in this, please help. If you have any re= sources around this do share them.

Hi, I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings. Is...

Hi, I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings. Is there any software I can use to transform state machines in VHDL into drawings? Thank you. Weng

Hello everyone, I have recently started working on a project using Ethernet in an FPGA and I am using the UDP protocol for communication between...

Hello everyone, I have recently started working on a project using Ethernet in an FPGA and I am using the UDP protocol for communication between the PC and the FPGA. The communication is happening point to point so I was wondering do I need ARP implementation in my stack or can I just broadcast the message. I am building a UDP stack but was wondering is ARP a necessary requirement. Also, the ...

Hi, In the working process for my private project, I use free Notepad++ to code VHDL code and appreciate it very much! Here is an example of...

Hi, In the working process for my private project, I use free Notepad++ to code VHDL code and appreciate it very much! Here is an example of how powerful Notepad++ is: In 27 files, I easily found that I use the statement "when others => null; " 119 times and the statement "end case;" 117 times. There are certainly 2 mismatches for the 2 types of statements. I found only 1 mismat