Request for an example in Verilog

Started by Bitan Mallik in comp.arch.fpga7 months ago

Dear All, I am a student with primitive experience in verilog. I have a small verific= ation task for a top module. I have simplified the task...

Dear All, I am a student with primitive experience in verilog. I have a small verific= ation task for a top module. I have simplified the task in the below descri= ption, so that you can give me a quick response. There could be solve for t= his problem in various ways. But ideally I am finding a solution to create = an automatic test setup. Please find below the problem. If you could wri...


UART receiver

Started by promach in comp.arch.fpga7 months ago 1 reply

Hi, I am working on UART receiver. As of now, I am stucked at http://paste.ubuntu.com/25720292/ I could not find a proper hardware writing style...

Hi, I am working on UART receiver. As of now, I am stucked at http://paste.ubuntu.com/25720292/ I could not find a proper hardware writing style to continue with line 14 the overall hierarchy : https://i.imgur.com/lVEtKXT.png module sampling_strobe_generator(clk, start_detected, sampling_strobe); // produces sampling signal for the incoming Rx input clk, start_detected; output r...


Artix-7 boards

Started by john in comp.arch.fpga8 months ago 2 replies

Has anyone had any experience of using these...

Has anyone had any experience of using these : http://www.robotshop.com/uk/cmod-a7-35t-breadboardable-artix-7-fpga-module.ht ml?gclid=EAIaIQobChMIkqXI9rje1gIVxZkbCh2l_AkhEAEYASAAEgLo_PD_BwE They aren't in stock yet but maybe some have been shipped. I'm looking for comments on them for use with novice FPGA users. Anything you have to say may be helpful as I'm looking to buy a few of them....


Xilinx Platform cable USB and impact on linux without windrvr

Started by Michael Gernoth in comp.arch.fpga8 months ago 23 replies

Hello, after being bitten by windrvr once again (it did not compile after a kernel upgrade), I decided to see if I could get the Xilinx USB...

Hello, after being bitten by windrvr once again (it did not compile after a kernel upgrade), I decided to see if I could get the Xilinx USB cable and impact working without a kernel module. To achieve this, I have written a wrapper library for impact which maps calls to windrvr to the userspace libusb-library which should be available on all modern linux distributions. With this wrapper I...


Re: Help finding Xilinx software for HW-130 programmer

Started by Rob M in comp.arch.fpga8 months ago

responding to http://www.electrondepot.com/fpga/help-finding-xilinx-software-for-hw-130-programmer-81804-.htm , Rob M wrote: > TimRegeant ...

responding to http://www.electrondepot.com/fpga/help-finding-xilinx-software-for-hw-130-programmer-81804-.htm , Rob M wrote: > TimRegeant wrote: > > On 12/5/2016 10:37 PM, Joe Z wrote: > > responding to > > > http://www.electrondepot.com/fpga/help-finding-xilinx-software-for-hw-130-programmer-81804-.htm > > > > > , Joe Z wrote: > > > gnuarm wrote: > > > > > > On 5/3/2016 2:23


duty cycle of clock divider

Started by promach in comp.arch.fpga8 months ago 8 replies

http://www.fpga4fun.com/MusicBox1.html The frequency is 440Hz, as expected, but the output duty cycle is not 50% anymore. The low level goes...

http://www.fpga4fun.com/MusicBox1.html The frequency is 440Hz, as expected, but the output duty cycle is not 50% anymore. The low level goes from counter=0 to counter=32767 (when bit 15 of counter is low) and then high level from 32768 to 56817. That gives us "speaker" being high only 42% of the time. The easiest way to get a 50% duty cycle is to add a stage that divides the out


logic scope coding

Started by promach in comp.arch.fpga8 months ago 1 reply

Could anyone give general comments on https://github.com/promach/internal_logic_analyzer/tree/development/rtl ? Is my coding approach too...

Could anyone give general comments on https://github.com/promach/internal_logic_analyzer/tree/development/rtl ? Is my coding approach too software-centric ?


registers delay

Started by promach in comp.arch.fpga9 months ago 1 reply

for the case of registers dependencies, d

for the case of registers dependencies, d


Microsemi FPGAs

Started by John Larkin in comp.arch.fpga9 months ago 3 replies

Has anyone used the Microsemi SOCs, the SmartFusion2 FPGAs with an ARM Cortex M3 on chip? How good/awful is the tool set? Any big likes or...

Has anyone used the Microsemi SOCs, the SmartFusion2 FPGAs with an ARM Cortex M3 on chip? How good/awful is the tool set? Any big likes or dislikes? They look like a pretty good deal for a medium FPGA with ARM. -- John Larkin Highland Technology, Inc lunatic fringe electronics


Article about using Non-Project Mode

Started by Ilya Kalistru in comp.arch.fpga9 months ago 11 replies

Hi! During the discussion about "Test Driven Design?" I promised to write a paper about Non-Project Mode and how it helps with testing. The...

Hi! During the discussion about "Test Driven Design?" I promised to write a paper about Non-Project Mode and how it helps with testing. The problem is that I have never written any article. Moreover, English is not my native language. I kindly ask you to review the article and help me to improve it. It is in Google docs and leaving comments right in the document is allowed. You also can comment...


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