glitching AND gate

Started by David Bridgham in comp.arch.fpga2 months ago 25 replies

I have a question about how FPGAs handle signals into combinational logic. I have following setup: always @(posedge interrupt_check)...

I have a question about how FPGAs handle signals into combinational logic. I have following setup: always @(posedge interrupt_check) interrupt_detect


RISC-V Support in FPGA

Started by rickman in comp.arch.fpga2 months ago 62 replies

I don't recall where, but there was a conversation recently about using the RISC-V in FPGAs. Thought I'd pass on the...

I don't recall where, but there was a conversation recently about using the RISC-V in FPGAs. Thought I'd pass on the link. https://www.microsemi.com/products/fpga-soc/technology-solutions/embedded-processing/risc-v -- Rick C


Lattice ECP5 succesor ( with DDR4 phy) ?

Started by Brane2 in comp.arch.fpga2 months ago 4 replies

AFAIK ECP5 is good for interfacing with DDR3, but not DDR4. Is there a plan to introduce new members with DDR4 or perhaps new family with such...

AFAIK ECP5 is good for interfacing with DDR3, but not DDR4. Is there a plan to introduce new members with DDR4 or perhaps new family with such interface ?


POLL: Would you want to know?

Started by Rick C. Hodgin in comp.arch.fpga2 months ago 30 replies

I have said previously I would not post in this group about Jesus any longer. But I fear I have sinned against God in making that statement. ...

I have said previously I would not post in this group about Jesus any longer. But I fear I have sinned against God in making that statement. So, I want to ask a poll: Question: If you were wrong in your belief that we do not need Jesus to forgive us of sin ... would you want to know? Please answer yes or no: Yes -- You WOULD want to know if you were wrong. ...


When I'm Wrong I'd Like to Know

Started by rickman in comp.arch.fpga3 months ago 1 reply

But each topic I'm wrong about should be addressed in that newsgroup. If I were wrong about something related to FPGAs (just an imaginary...

But each topic I'm wrong about should be addressed in that newsgroup. If I were wrong about something related to FPGAs (just an imaginary example, of course) I wouldn't want it discussed in alt.religion.emacs. Likewise I don't wish for things not related to FPGAs to be discussed here. Every discussion in its place! Is there any chance the person this post is directed to will actually ...


creating a seed on a FPGA.

Started by kristoff in comp.arch.fpga3 months ago 6 replies

Hi, I am aware that the best way to create a seed (for random numbers) is external hardware, but does anybody know any cheap-and-easy tricks...

Hi, I am aware that the best way to create a seed (for random numbers) is external hardware, but does anybody know any cheap-and-easy tricks to generate a random-ish number on an FPGA. Kristoff


Cyclotomic FFTs

Started by Kevin Neilson in comp.arch.fpga3 months ago

I've been researching cyclotomic FFTs. There is a lot of literature (Fedorenko, Trifinov, Costa, etc.) about using this technique for calculating...

I've been researching cyclotomic FFTs. There is a lot of literature (Fedorenko, Trifinov, Costa, etc.) about using this technique for calculating the syndrome and doing the Chien Search in Reed-Solomon decoders. I'd like to know if anybody has actually used this in hardware. The literature makes bold claims about the massive 100x efficiency gains, but it seems like it's only usef


FPGA as heater

Started by John Larkin in comp.arch.fpga3 months ago 50 replies

We have a ZYNQ whose predicted timing isn't meeting decent margins. And we don't want a lot of output pin timing variation in real life. We...

We have a ZYNQ whose predicted timing isn't meeting decent margins. And we don't want a lot of output pin timing variation in real life. We can measure the chip temperature with the XADC thing. So, why not make an on-chip heater? Use a PLL to clock a bunch of flops, and vary the PLL output frequency to keep the chip temp roughly constant. -- John Larkin Highland Technology, ...


Master Xilinx FPGA like Jtag bridge.

Started by Anonymous in comp.arch.fpga3 months ago 10 replies

How to make master FPGA to connect to many FPGAs ? Two FPGAs connected by serial TDI - TDO, and two fpgas TMS TCK TDO and TDI connect to...

How to make master FPGA to connect to many FPGAs ? Two FPGAs connected by serial TDI - TDO, and two fpgas TMS TCK TDO and TDI connect to master fpga, master fpga has TMS TDI TDO TCK connected and working to pc normally, it need to make connection JTAG of two fpgas to other 4 ports or somehow can connect to master's jtag port ?


how to convert analog signal cccam video to digital using systemc

Started by Anonymous in comp.arch.fpga3 months ago 1 reply

Hi In the context of a university research, I try to convert the signal coming from an analog camera (1000tvl camera style) to obtain a digital...

Hi In the context of a university research, I try to convert the signal coming from an analog camera (1000tvl camera style) to obtain a digital signal and save it in a file in format h264; All using SYSTEMC. RQ: I start in systemc Someone can help me or guide me. thank you


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