Fixed Point Arithmetic

Started by gnua...@gmail.com in comp.arch.fpga9 months ago 9 replies

I don't know why I thought it would be easy. The arithmetic is not so hard by itself. But changing all the equations to normalize the variables...

I don't know why I thought it would be easy. The arithmetic is not so hard by itself. But changing all the equations to normalize the variables is not so easy. Then there is the issue of needing to assure the results don't grow out of range and I hadn't even given thought to the need for saturating arithmetic in some cases. I'm designing a fixed point math engine to do modera


PHB FPGA question

Started by Anonymous in comp.arch.fpga9 months ago 3 replies

OK, pointy-haired boss question. Given a ZYNQ 7020, speed grade 1. A 3.3 volt i/o bank gets a clock from an LVDS input. We have a resync flop...

OK, pointy-haired boss question. Given a ZYNQ 7020, speed grade 1. A 3.3 volt i/o bank gets a clock from an LVDS input. We have a resync flop in an i/o cell, clocked by this, with a D input from somewhere. Output is the strongest/fastest 3.3 volt option. About what would be the typical prop delay from the clock to the output pin? Online search yields a lot of words and no numbers. Exp...


Temperature Sensor Error

Started by Mezanur Rahman in comp.arch.fpga9 months ago 6 replies

Hi everyone, I'm trying to implement the following code on the NEXYS A7 board and it seems the I2C communication isn't working...

Hi everyone, I'm trying to implement the following code on the NEXYS A7 board and it seems the I2C communication isn't working properly. https://github.com/bdeloeste/Nexys-4-Temperature-Sensor--ADT-7420/blob/master/VGA%20Module/vga_t emp_sensor.srcs/sources_1/new/I2C_temp.v this my constraint file ===================================> ## clock set_property -dict { PACKAGE_PIN E3 IOSTAN


CRC is an FPGA PITA

Started by gnua...@gmail.com in comp.arch.fpga9 months ago 18 replies

I had a newbie working on a bit wise CRC32 implementation and he could not = get the results of any of the many online CRC32 generators...

I had a newbie working on a bit wise CRC32 implementation and he could not = get the results of any of the many online CRC32 generators available. So I= coded up the same algorithm and tried it myself with similar results. =20 I tried digging around and found little that I could use to either evaluate= an algorithm or to generate comparison data other than the final result. = What I nee...


Why am I getting different results with two files collapsed into one?

Started by Kevin Simonson in comp.arch.fpga10 months ago 5 replies

I wrote a Verilog file: [code] // (c) 2020 Kevin Simonson module equ2 ( output result , output nrOut , output xwOut , input leftOp ...

I wrote a Verilog file: [code] // (c) 2020 Kevin Simonson module equ2 ( output result , output nrOut , output xwOut , input leftOp , input rightOp); wire notRight, xorWeak; supply1 power; supply0 ground; nmos #(3) nRg( notRight, ground , rightOp); pmos #(3) pRg( notRight, power , rightOp); nmos #(3) nXor( xorWeak , notRight, leftOp ); pmos #(3) pXor( xorWeak , ...


Synthesizable open FPGA cores

Started by partha sarathy in comp.arch.fpga10 months ago 1 reply

Hi Experts, I am looking for Synthesizable FPGA (Xilinx) SOC cores like RUSC-V etc ( more than 100K LUTs) for evaluating their timing...

Hi Experts, I am looking for Synthesizable FPGA (Xilinx) SOC cores like RUSC-V etc ( more than 100K LUTs) for evaluating their timing performance. Could you please point me to their repositories ? Best


To Reset or not to Reset, That is the Question!

Started by gnua...@gmail.com in comp.arch.fpga10 months ago 4 replies

Whether tis nobler to suffer the slings and arrows of outrageous judgement = or just add the pointless, incorrectly working async reset that...

Whether tis nobler to suffer the slings and arrows of outrageous judgement = or just add the pointless, incorrectly working async reset that every frigg= in' text book and every training example shows. =20 I'm on a project where we have no strong guidance and one member of the tea= m is the type who *knows* how to work a project and so has zero interest in= considering what others are doin...


Using DSP Units

Started by gnua...@gmail.com in comp.arch.fpga10 months ago 7 replies

I working with the Gowin GW1N devices and need to do some serious math. By= serious, I mean a number of calculations, not that they have to be...

I working with the Gowin GW1N devices and need to do some serious math. By= serious, I mean a number of calculations, not that they have to be fast. = In fact, I pretty much have all the time in the world relatively speaking. = The cycle time for performing all the calculations is 5 ms with a 33 MHz c= lock, so 167,000 odd cycles. =20 What I'm not up to speed about is just how to use or...


Programming a Traffic Light Controller In verilog using Quartus Prime Lite

Started by Dave Wood in comp.arch.fpga10 months ago 3 replies

Hi everyone, ( Don't know if this is even the right place to post a question but ill tr= y my luck) So basically I am a student and I have a...

Hi everyone, ( Don't know if this is even the right place to post a question but ill tr= y my luck) So basically I am a student and I have a final project to build a traffic l= ight control system using Verilog, and then I am to program my FPGA board w= hich is a De10-lite. I feel like the coding aspect of the project isn't bad= . I have cases and such set up to switch the device to differe...


ADCs in FPGAs

Started by Rick C in comp.arch.fpga10 months ago 23 replies

I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all digitally, or almost so. I'm...

I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all digitally, or almost so. I'm not completely clear on how to do it. Lattice has a reference design using an LVDS receiver as a comparator. They use an RC filter on the output bit as the reference voltage for the input. I'm having trouble relating this to the typ


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