Need magic incantation to prevent synthesizer misoptimisation

Started by Aleksandar Kuktin in comp.arch.fpga5 months ago 2 replies

Hi all! I'm having a problem with the synthesis and P&R tools introducing a unnecessary gate in a critical path. Consider the following...

Hi all! I'm having a problem with the synthesis and P&R tools introducing a unnecessary gate in a critical path. Consider the following verilog: reg [31:0] mem_dataintomem = 32'd0; always @(posedge CLK) begin if (mcu_active && (w_we_recv || w_tlb_recv)) mem_dataintomem


Schematic FPGA Design on twitch

Started by Anonymous in comp.arch.fpga6 months ago 2 replies

tomorrow from 20:15 cet until open end live on my channel https://www.twitch.tv/fpga_guru schematic design on fpga. check it out

tomorrow from 20:15 cet until open end live on my channel https://www.twitch.tv/fpga_guru schematic design on fpga. check it out


Need Help regarding I2C Protocol testbench

Started by Swapnil Patil in comp.arch.fpga6 months ago 1 reply

Hello folks, I am trying to get a VHDL testbench running with the VHDL I2C core model. I am using spartan 6 fpga and using a simple state...

Hello folks, I am trying to get a VHDL testbench running with the VHDL I2C core model. I am using spartan 6 fpga and using a simple state machine. The problem with simulation result is that it is writing data properly but not reading it.I do not understand what is problem? here is my testbench Data in sent internally via array. ENTITY mainfiletb12 IS END mainfiletb12; ARCHITECTUR...


Need Advice regarding Interfacing of Max9850 audio DAC with spartan 6 FPGA

Started by Swapnil Patil in comp.arch.fpga6 months ago 1 reply

Hello Folks, I am trying to interface MAX9850 Audio DAC with spartan 6 FPGA with I2C Interfacing. I'm Using VHDL Language For coding. Does...

Hello Folks, I am trying to interface MAX9850 Audio DAC with spartan 6 FPGA with I2C Interfacing. I'm Using VHDL Language For coding. Does Someone worked on this before? or worked related to this. Things need to know I am using only these two for interfacing.So For clocking what should i do?(can i use fpga clock for driving master clock) what audio data format to choose?Right justifie...


System Verilog Import package error

Started by nikh...@gmail.com in comp.arch.fpga6 months ago

Hello, I have a few packages that I have written like this: package A; -- -- endpackage package B; import A::* --- --...

Hello, I have a few packages that I have written like this: package A; -- -- endpackage package B; import A::* --- -- endpackage package C; import A::*; import B::*; endpackage In the file using package C, the error I am getting is as follows: Error (10864): SystemVerilog error at C.sv(26): TMP was imported from multiple packages with ::* - none of the imported declaratio...


Cheaptest FPGA board for Computer Architecture

Started by Othman Ahmad in comp.arch.fpga7 months ago 4 replies

http://mymicroprocessor.blogspot.com/2018/08/cheapest-fpga-board-rm250-similar-to.html The A-CE4E6 Intel Cyclone IV FPGA ic.

http://mymicroprocessor.blogspot.com/2018/08/cheapest-fpga-board-rm250-similar-to.html The A-CE4E6 Intel Cyclone IV FPGA ic.


FPGA simplest processor

Started by Anonymous in comp.arch.fpga7 months ago 7 replies

http://mymicroprocessor.blogspot.com/2018/08/fpga-simplest-processor.html Go to my blog for more information.

http://mymicroprocessor.blogspot.com/2018/08/fpga-simplest-processor.html Go to my blog for more information.


PipelineC

Started by Julian Kemmerer in comp.arch.fpga8 months ago

Hi folks, I have a little project I've been working on to make a better HDL-like language. It's a subset of C so should be familiar. I am...

Hi folks, I have a little project I've been working on to make a better HDL-like language. It's a subset of C so should be familiar. I am using a Digilent Arty Artix-35T board and have a working UDP example. I am looking for opinions on current progress and ideas for what features/projects to pursue next. Also, if you like correcting bad python - heyo! Check it out eh: https://g...


8 bits vs. 9 bits in RAM Blocks

Started by Anonymous in comp.arch.fpga8 months ago 5 replies

The Xilinx, Altera/Intel and the mainline Lattice devices all support RAM blocks in widths of multiples of 9 bits. Some other devices only have...

The Xilinx, Altera/Intel and the mainline Lattice devices all support RAM blocks in widths of multiples of 9 bits. Some other devices only have RAM widths of multiples of 8 bits or less. Does this make much of a difference to you? Do you use the 9 bit widths in your designs? Rick C.


Stepper motor controller

Started by Anonymous in comp.arch.fpga9 months ago 2 replies

Hello all, I used Hamsterwork's http://hamsterworks.co.nz/mediawiki/index.php/Stepper stepper motor controller , there position out for leds etc....

Hello all, I used Hamsterwork's http://hamsterworks.co.nz/mediawiki/index.php/Stepper stepper motor controller , there position out for leds etc. How i can make give position back.. I.E. I want to give position to stepper motor controller not push a button.. could some one help me with code ?


Ask a Question to the FPGARelated community

To significantly increase your chances of receiving answers, please make sure to:

  1. Use a meaningful title
  2. Express your question clearly and well
  3. Do not use this forum to promote your product, service or business
  4. Write in clear, grammatical, correctly-spelled language
  5. Do not post content that violates a copyright