How to turn off cursor note pane when cursor stops at wave pane of ModelSim

Started by Tianxiang Weng in comp.arch.fpga1 year ago 2 replies

Hi, How to turn off the cursor note pane when the cursor stops at the wave pane of ModelSim during simulation? A cursor note pane is shown at...

Hi, How to turn off the cursor note pane when the cursor stops at the wave pane of ModelSim during simulation? A cursor note pane is shown at the wave pane of ModelSim with yellow background color when the cursor stops at a signal line, showing the signal path and name. Thank you. Weng


Intel ModelSim Starter Edition is available free now!

Started by W TX in comp.arch.fpga1 year ago 18 replies

Hi, Intel ModelSim Starter Edition is available free now! https://fpgasoftware.intel.com/ 10,000 line code limit, VHDL-2002 version,...

Hi, Intel ModelSim Starter Edition is available free now! https://fpgasoftware.intel.com/ 10,000 line code limit, VHDL-2002 version, running speed is very very slow, but it is enough for debugging grammars. It needs to take 3 hours to download Starter Edition part 1 and part 2 of 7.3G, regardless of how your download speed is. Weng


Using MachXO2 as a SRAM device

Started by Piotr Wyderski in comp.arch.fpga1 year ago

Hi, I have an application where replacing the configuration of the FPGA will occur frequently and hence I do not want to use the built-in...

Hi, I have an application where replacing the configuration of the FPGA will occur frequently and hence I do not want to use the built-in FLASH. Having an always-blank device on the board is perfectly fine. The MachXO2 chip is ideal for many reasons, so I don't want to replace it with a purely SRAM-based FPGA. Now, the "MachXO2 Programming and Configuration Usage Guide" says the FL...


VHDL2019 Webinars

Started by HT-Lab in comp.arch.fpga1 year ago 8 replies

In case you missed it Aldec (Jim Lewis) is doing a webinars series on VHDL2019. https://www.aldec.com/en/company/events It looks like I...

In case you missed it Aldec (Jim Lewis) is doing a webinars series on VHDL2019. https://www.aldec.com/en/company/events It looks like I missed the first one as it start with Part2, Regards, Hans. www.ht-lab.com


A bewildering Visio-2019 problem!

Started by W TX in comp.arch.fpga1 year ago 1 reply

Unfortunately, I met a bewildering problem with Visio-2019. I have been using Visio-2019 to make circuit drawings, everything goes well until...

Unfortunately, I met a bewildering problem with Visio-2019. I have been using Visio-2019 to make circuit drawings, everything goes well until yesterday. I modified a drawing, and generated a PDF file, after that I used a merging software to merge a set of PDF drawings into one PDF file. When I opened the collected PDF file a strange thing happens: the collected PDF file could not sh


Research Assistantship (Fall, 2021) at Dept. of Computer Engineering, Hallym University, Korea

Started by jg.lee in comp.arch.fpga1 year ago

Research Assistantship (Fall, 2021) at the Graduate School, Dept. of Comput= er Engineering, Hallym University, Korea The [AI Accelerator...

Research Assistantship (Fall, 2021) at the Graduate School, Dept. of Comput= er Engineering, Hallym University, Korea The [AI Accelerator Design Lab] of the Hallym University seek to recruit pr= omising PhD and MSc or MSc-PhD research students. The selected students will conduct research in the [Hardware Implementation= of Deep Learning Algorithms] and [Deep Learning for Medical Applicat...


XILINX PCIe read of slow device

Started by David Binette in comp.arch.fpga1 year ago 20 replies

What is the correct way to handle a PCIE request to a slow device? I have a xilinx spartan 6 PCIe using Integrated Block for PCI...

What is the correct way to handle a PCIE request to a slow device? I have a xilinx spartan 6 PCIe using Integrated Block for PCI Express. The BAR memory map is decoded and some addresses map to fast ram, or local registers and these work OK, but some addresses map to slow devices.. like I2C or internal processes that need a few cycles to process before they can produce valid data to be ret...


Hi can anyone please tell me how to rectify this error

Started by Shanmukharao Muddada in comp.arch.fpga1 year ago 1 reply

Hi can anyone please tell me how to rectify this error ERROR:MapLib:30 - LOC constraint J17 on topsegF is invalid: No such site on the ...

Hi can anyone please tell me how to rectify this error ERROR:MapLib:30 - LOC constraint J17 on topsegF is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:30 - LOC constraint H14 on topsegG is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:30 - ...


Achronix?

Started by John Larkin in comp.arch.fpga1 year ago 2 replies

Has anyone used Achronix FPGAs?

Has anyone used Achronix FPGAs?


MachXO2 pin mismatch error

Started by Piotr Wyderski in comp.arch.fpga1 year ago 1 reply

Hi, I am trying to use a PMI ROM memory block in Lattice Diamond/VHDL: decoder_rom0 : pmi_rom generic map ( pmi_addr_width => ...

Hi, I am trying to use a PMI ROM memory block in Lattice Diamond/VHDL: decoder_rom0 : pmi_rom generic map ( pmi_addr_width => 3, pmi_data_width => decoder_rom_data'length, pmi_regmode => "noreg", pmi_gsr => "disable", pmi_resetmode => "sync", pmi_optimization => "area", pmi_init_file => "i2c_decoder_rom.mem", pmi_init_file_format => "binary" )


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