sram

Started by kristoff in comp.arch.fpga9 months ago 44 replies

Hi, OK, left the lora chips asside for a while, so .. now back to FPGAs. I have two olimex ice40 boards where I would like to use the...

Hi, OK, left the lora chips asside for a while, so .. now back to FPGAs. I have two olimex ice40 boards where I would like to use the onboard SRAM. The RAM chip is a samsung K5R4016V1B-10 (256K words * 16 bits). The datasheets are here: https://www.olimex.com/Products/_resources/ds_k6r4016v1d_rev40.pdf The most important pages are page 7 (for "read"), pages 8 and 9 (for "write") a...


Microsemi SmartFusion2 Field Upgrade

Started by Rob Gaddi in comp.arch.fpga9 months ago 4 replies

We're starting a new design, and I again find myself tempted by the Microsemi SmartFusion2 as combination FPGA/uC. It's got a built-in ARM...

We're starting a new design, and I again find myself tempted by the Microsemi SmartFusion2 as combination FPGA/uC. It's got a built-in ARM Cortex-M3, which is a simple dinky micro instead of some big honking A8 application processor that you can't even get up and running without kilobytes of boot code. The smallest, cheapest one is about $15 in small quantity with 64 kB of data memory ...


Suggestion on methodology/ways to test my internal logic analyzer softcore modules

Started by promach in comp.arch.fpga9 months ago

Using http://zipcpu.com/blog/2017/06/08/simple-scope.html , I have rewritten my internal logic analyzer at...

Using http://zipcpu.com/blog/2017/06/08/simple-scope.html , I have rewritten my internal logic analyzer at https://github.com/promach/internal_logic_analyzer I want to know if my softcore logic scope works. What inputs, into that module, and outputs from it will prove to me that my scope module works?


SystemVerilog and alternatives

Started by tullio in comp.arch.fpga9 months ago 2 replies

Hello, i am an experienced FPGA designer, having used Verilog for long time. For a mixed analog-digital project involving an ASIC and (maybe)...

Hello, i am an experienced FPGA designer, having used Verilog for long time. For a mixed analog-digital project involving an ASIC and (maybe) an FPGA, i need to get ready for extensive verification and test-vector generation. The mainstream tools seem to be SystemVerilog and UVM, which seem to have a difficult learning curve and also difficult maintenance. But somebody suggested me to consi...


minimal HDMI pins to send video ?

Started by Anonymous in comp.arch.fpga10 months ago 7 replies

Dear all who knows 4 pairs of 1) CLOCK+, CLOCK- 2) TMDS2+, TMDS2- 3) TMDS1+, TMDS1- 4) TMDS0+, TMDS0- are enough to send video...

Dear all who knows 4 pairs of 1) CLOCK+, CLOCK- 2) TMDS2+, TMDS2- 3) TMDS1+, TMDS1- 4) TMDS0+, TMDS0- are enough to send video by HDMI or need to generate some other signals ?


What kit for SPARTAN-3?

Started by Borneq in comp.arch.fpga10 months ago

I have XILINX - XC3S4000 - 4FGG676I - SPARTAN-3 FPGA 4M STD 676-FBGA someone advise me XC6SLX9

I have XILINX - XC3S4000 - 4FGG676I - SPARTAN-3 FPGA 4M STD 676-FBGA someone advise me XC6SLX9


converting from Xilinx 9500 to 9500XL, won't fit

Started by Jon Elson in comp.arch.fpga10 months ago 2 replies

Hello, all, I have an old design implemented in the Xilinx 9572, and need to update it. Using ise 13.4, I created a new project, imported...

Hello, all, I have an old design implemented in the Xilinx 9572, and need to update it. Using ise 13.4, I created a new project, imported the files, and found it won't fit in the 9572XL, which was a big surprise. Although the 9572 was fairly full, the design easily fit there, and I just recompiled it for the 9572, and this version of ise easily fit it. Does anybody have any suggest...


IP core LCD controller for Zynq-7000 famiy

Started by Anonymous in comp.arch.fpga10 months ago

Do you know something about free IP cores for this fpga? Xylon IPs are too expensive for me. Cheers, ucy

Do you know something about free IP cores for this fpga? Xylon IPs are too expensive for me. Cheers, ucy


Ielts,Toefl, Pte, Esol, Toiec, Oet, Gmat, Gre, Nebosh, SAT, ACT, GED,

Started by velma niro in comp.arch.fpga11 months ago

Hi Friends You Have Problems in getting the required scores in Ielts,Toefl, Pte, Esol, Toiec, Oet, Gmat, Gre, Nebosh, SAT, ACT, GED,...

Hi Friends You Have Problems in getting the required scores in Ielts,Toefl, Pte, Esol, Toiec, Oet, Gmat, Gre, Nebosh, SAT, ACT, GED, Usmle, Psat, lsat, Celban, FCE, CAE,CPE, BEC, Fle, Tesol,??? Need Ielts certificate urgently in Australia, Saudi Arabia, Oman, Lebanon, Qatar, Canada, India, Dubai, Iran, Pakistan, Belarus, Kuwait, Germany, France, Anywhere... From British


consulting job / Xilinx Artix MGT POR

Started by Tobias Kahre in comp.arch.fpga11 months ago

Hi there, I am looking for an expert on how to by-hand-configure MGTs individually of an single quad. I have an Artix 35T, the first MGT has...

Hi there, I am looking for an expert on how to by-hand-configure MGTs individually of an single quad. I have an Artix 35T, the first MGT has to do aurora, the second and third one has to do JESD204b. I am offering a consulting fee for teaching me personally and/or working design of POR up to exchange of comma characters. Cheers, Tobias


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