Passing digitized data to design

Started by Mohammed Billoo in comp.arch.fpga10 months ago 5 replies

Hello, Is there a resource that can help me understand how to pass digitized data (from a waveform) to a design that I have for verification?...

Hello, Is there a resource that can help me understand how to pass digitized data (from a waveform) to a design that I have for verification? I'm getting into FPGA development and have created a simple filter. I wanted to test it out on audio data that I can generate and see that the filter actually works, but I haven't found a way to actually "pass" data to a design. Thanks Moh


coronavirus COVID-19

Started by Anonymous in comp.arch.fpga11 months ago

coronavirus COVID-19 http://www.grex.org/~henced/coronavirus.html

coronavirus COVID-19 http://www.grex.org/~henced/coronavirus.html


CFP IEEE International Conference on Computer Design (ICCD) 2020

Started by Pillement in comp.arch.fpga11 months ago

------------------------------------------------------------------ Call for...

------------------------------------------------------------------ Call for Papers ------------------------------------------------------------------ 2020 IEEE International Conference on Computer Design (ICCD) Oct 18-21, 2020 Hartford, Connecticut USA -----------------------------------------------------------...


No more gate-level simulation. for Cyclone V !!!

Started by Luis Cupido in comp.arch.fpga11 months ago 8 replies

Hello, I'm dealing with some fast state machines and gate-level-timing simulation of some components has been very helpful. Now using a...

Hello, I'm dealing with some fast state machines and gate-level-timing simulation of some components has been very helpful. Now using a Cyclone V I found that I can't do timing gate-level timing simulation, quartus does not generate the SDF file, the *.sdo file. Altera/Intel says this on the documentation regarding simulation: "Gate-level timing simulation is supported only for the...


Terminated

Started by Jeff Hickling in comp.arch.fpga11 months ago 2 replies

2017 Dennis terminated from the Public Library. Failure to perform guard duties. Last week, the week of June 19th, Dennis was summarily...

2017 Dennis terminated from the Public Library. Failure to perform guard duties. Last week, the week of June 19th, Dennis was summarily discharged from his position of library security guard by new interim librarian, apparently a young woman not to be ?truffled? with. The new librarian cited the primary reason for Officer D?s summary dismissal as a ?failure to act in accorda


Fight the coronavirus 100% and save LOTS of CASH -- Combattez le coronavirus 100% et économisez BEAUCOUP d'ARGENT

Started by Anonymous in comp.arch.fpga11 months ago

Protect yourself and your loved ones ! KILL the coronavirus right now ! And save LOTS OF CASH New tested, scientificly proven and amazing...

Protect yourself and your loved ones ! KILL the coronavirus right now ! And save LOTS OF CASH New tested, scientificly proven and amazing antivirus against coronavirus using Chloroquine and Colchicine at very low price (33% discount) Satisfaction garanteed or your money back ! http://als0p.atwebpages.com/coronavirus/coronavirus-en.php Prot?gez-vous et vos proches! TUEZ le coronavirus...


Use example of Intel University program in Intel Quartus - problem with Board support package?

Started by Bliad Bors in comp.arch.fpga11 months ago 4 replies

I want to use a example from the Intel FPGA Monitor Program 18.1 and use it in Quartus 18.1. It is the video example, which creates a blue box...

I want to use a example from the Intel FPGA Monitor Program 18.1 and use it in Quartus 18.1. It is the video example, which creates a blue box on the HDMI output and writes a littel String with white letters on top of it. I want to use it in Intel Quartus environment , do some test-outputs on my screen and finally add some more Hardware to the Avalon system. Unfortunately it doe


PipelineC - C-like almost hardware description language - AWS F1 Example

Started by Julian Kemmerer in comp.arch.fpga11 months ago 2 replies

Hi folks, Here to talk about PipelineC. https://github.com/JulianKemmerer/PipelineC/wiki What is it?: - C-like almost hardware description...

Hi folks, Here to talk about PipelineC. https://github.com/JulianKemmerer/PipelineC/wiki What is it?: - C-like almost hardware description language - A compiler that produces VHDL for specific devices/operating frequencies I am looking for: - anyone who wants to help me develop (Python, VHDL, C) - suggestions on how to make PipelineC more useful/new features - project ideas (heyo open...


Using EDA tools at home

Started by Anonymous in comp.arch.fpga12 months ago

Need to use your company EDA tools from home, here are some tips: 1) First of all, the most important solution is to speak to your EDA...

Need to use your company EDA tools from home, here are some tips: 1) First of all, the most important solution is to speak to your EDA vendor= , I am sure all have solutions for you and some even give you a free tempor= ary license (if you are an existing customer). 2) If you have a node locked license, simply take the dongle home. 3) If you have a MAC based license then try to spoof the MA...


Code block in icestudio

Started by Josef Moellers in comp.arch.fpga1 year ago 17 replies

Hi, I'm trying to program a TinyFPGA BX to provide 3 registers to emulate an FDC9266, the bulk will later be done using an ATMega...

Hi, I'm trying to program a TinyFPGA BX to provide 3 registers to emulate an FDC9266, the bulk will later be done using an ATMega ucontroller. To sort out the A0,nCS,nRD,nWR,nDACK, I have inserted a code block which should generate the following internal signals: SEL: switch a "Mux 2:1" between the outputs of the STATUS and the DATA IN registers OE: enable a TRI-STATE output to the pr...


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