Why am I getting different results with two files collapsed into one?

Started by Kevin Simonson in comp.arch.fpga1 year ago 5 replies

I wrote a Verilog file: [code] // (c) 2020 Kevin Simonson module equ2 ( output result , output nrOut , output xwOut , input leftOp ...

I wrote a Verilog file: [code] // (c) 2020 Kevin Simonson module equ2 ( output result , output nrOut , output xwOut , input leftOp , input rightOp); wire notRight, xorWeak; supply1 power; supply0 ground; nmos #(3) nRg( notRight, ground , rightOp); pmos #(3) pRg( notRight, power , rightOp); nmos #(3) nXor( xorWeak , notRight, leftOp ); pmos #(3) pXor( xorWeak , ...


Synthesizable open FPGA cores

Started by partha sarathy in comp.arch.fpga1 year ago 1 reply

Hi Experts, I am looking for Synthesizable FPGA (Xilinx) SOC cores like RUSC-V etc ( more than 100K LUTs) for evaluating their timing...

Hi Experts, I am looking for Synthesizable FPGA (Xilinx) SOC cores like RUSC-V etc ( more than 100K LUTs) for evaluating their timing performance. Could you please point me to their repositories ? Best


To Reset or not to Reset, That is the Question!

Started by gnua...@gmail.com in comp.arch.fpga1 year ago 4 replies

Whether tis nobler to suffer the slings and arrows of outrageous judgement = or just add the pointless, incorrectly working async reset that...

Whether tis nobler to suffer the slings and arrows of outrageous judgement = or just add the pointless, incorrectly working async reset that every frigg= in' text book and every training example shows. =20 I'm on a project where we have no strong guidance and one member of the tea= m is the type who *knows* how to work a project and so has zero interest in= considering what others are doin...


Using DSP Units

Started by gnua...@gmail.com in comp.arch.fpga1 year ago 7 replies

I working with the Gowin GW1N devices and need to do some serious math. By= serious, I mean a number of calculations, not that they have to be...

I working with the Gowin GW1N devices and need to do some serious math. By= serious, I mean a number of calculations, not that they have to be fast. = In fact, I pretty much have all the time in the world relatively speaking. = The cycle time for performing all the calculations is 5 ms with a 33 MHz c= lock, so 167,000 odd cycles. =20 What I'm not up to speed about is just how to use or...


Programming a Traffic Light Controller In verilog using Quartus Prime Lite

Started by Dave Wood in comp.arch.fpga1 year ago 3 replies

Hi everyone, ( Don't know if this is even the right place to post a question but ill tr= y my luck) So basically I am a student and I have a...

Hi everyone, ( Don't know if this is even the right place to post a question but ill tr= y my luck) So basically I am a student and I have a final project to build a traffic l= ight control system using Verilog, and then I am to program my FPGA board w= hich is a De10-lite. I feel like the coding aspect of the project isn't bad= . I have cases and such set up to switch the device to differe...


ADCs in FPGAs

Started by Rick C in comp.arch.fpga1 year ago 23 replies

I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all digitally, or almost so. I'm...

I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all digitally, or almost so. I'm not completely clear on how to do it. Lattice has a reference design using an LVDS receiver as a comparator. They use an RC filter on the output bit as the reference voltage for the input. I'm having trouble relating this to the typ


Is there a way in Verilog to refer to a slice of an array?

Started by Kevin Simonson in comp.arch.fpga1 year ago 9 replies

I've got two Verilog modules that look like this: module queue ( output [ 64:0] dataOut , input reset , input ...

I've got two Verilog modules that look like this: module queue ( output [ 64:0] dataOut , input reset , input shift , input [ 64:0] dataIn); ... endmodule and module lessThan ( output lssThn , input [ 48:0] leftOp , input [ 48:0] rightOp); ... endmodule I've got six instances of module (queue) and need to pipe the forty-nine mo= st si...


Finally! I figgured it out accidentally.

Started by Rick C in comp.arch.fpga1 year ago 2 replies

Sometimes the tools are hard to figure out. I've been looking for a way to leave my source files in MY source directory rather than in the...

Sometimes the tools are hard to figure out. I've been looking for a way to leave my source files in MY source directory rather than in the Active-HDL source directory buried down in the bowels of their extraneous files directories. I was having a problem with the tool that i think is going to require rebooting the machine and rather than do that I'm working around not being abl


Is there a way in Verilog to refer to a slice of an array?

Started by Kevin Simonson in comp.arch.fpga1 year ago

I've got two Verilog modules that look like this: module queue ( output [ 64:0] dataOut , input reset , input ...

I've got two Verilog modules that look like this: module queue ( output [ 64:0] dataOut , input reset , input shift , input [ 64:0] dataIn); ... endmodule and module lessThan ( output lssThn , input [ 48:0] leftOp , input [ 48:0] rightOp); ... endmodule I've got six instances of module (queue) and need to pipe the forty-nine mo= st si...


HP "owning" the software for Xilinx-FTDI drivers???

Started by Rick C in comp.arch.fpga1 year ago 6 replies

Someone new on the project is talking about how HP owns the driver code for= the FTDI JTAG chip used to program Xilinx parts. Has anyone heard...

Someone new on the project is talking about how HP owns the driver code for= the FTDI JTAG chip used to program Xilinx parts. Has anyone heard of this= ? =20 Even if that is true, I'm not sure how relevant it is. Is there some issue= with HP owning the software for FTDI devices even if that is true? Why wo= uld it matter to a user of Xilinx FPGAs??? I did try getting an answer and f...


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