## Forums More comp.arch.fpga

## Fully Comitted to LVDS as Comparitors

I working on a design where there will be some five sigma-delta ADCs and several specific level detect inputs each using an LVDS input pair as a...

I working on a design where there will be some five sigma-delta ADCs and several specific level detect inputs each using an LVDS input pair as a comparator. So I'm pretty committed to this working. The LVDS common mode range can work down to 50 mV and I"ll be testing that. I need to sense the voltage across a FET in an H bridge for over current or open load. The ADCs need to have decen...

## Gowin - This Just Got Real

inI've been watching the various FPGA startup companies and a couple have pro= duct available through mainstream distributors. The one I like the...

I've been watching the various FPGA startup companies and a couple have pro= duct available through mainstream distributors. The one I like the most is= Gowin because of the easy to use packages they offer, 100QFP, 88QFN, etc. = I'm working on a ventilator project and have specified a Gowin part for th= at for many of the same reasons that I would use it myself. =20 Now a customer has as...

## Division Algorithms

inI am looking for an algorithm to calculate a floating point divide. There a= re a number of options, but the one that is most clear to me and...

I am looking for an algorithm to calculate a floating point divide. There a= re a number of options, but the one that is most clear to me and easiest to= implement on the hardware I am designing seems to be the Newton=E2=80=93Ra= phson iterative method. I'm trying to understand how many iterations it wil= l take. The formula for that in the Wikipedia article assumes an initial es= timate for...

## Achronix Semiconductor in Talks for Merger

inAn IPO of sorts really. They would merge with ACE Convergence Acquisition Corp NASDAQ: ACEV and this company would be seeking investors. ...

An IPO of sorts really. They would merge with ACE Convergence Acquisition Corp NASDAQ: ACEV and this company would be seeking investors. Achronix has been profitable, so this should be a good deal. I'm looking to buy in. -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209

## Fixed Point Arithmetic

inI don't know why I thought it would be easy. The arithmetic is not so hard by itself. But changing all the equations to normalize the variables...

I don't know why I thought it would be easy. The arithmetic is not so hard by itself. But changing all the equations to normalize the variables is not so easy. Then there is the issue of needing to assure the results don't grow out of range and I hadn't even given thought to the need for saturating arithmetic in some cases. I'm designing a fixed point math engine to do modera

## PHB FPGA question

inOK, pointy-haired boss question. Given a ZYNQ 7020, speed grade 1. A 3.3 volt i/o bank gets a clock from an LVDS input. We have a resync flop...

OK, pointy-haired boss question. Given a ZYNQ 7020, speed grade 1. A 3.3 volt i/o bank gets a clock from an LVDS input. We have a resync flop in an i/o cell, clocked by this, with a D input from somewhere. Output is the strongest/fastest 3.3 volt option. About what would be the typical prop delay from the clock to the output pin? Online search yields a lot of words and no numbers. Exp...

## Temperature Sensor Error

inHi everyone, I'm trying to implement the following code on the NEXYS A7 board and it seems the I2C communication isn't working...

Hi everyone, I'm trying to implement the following code on the NEXYS A7 board and it seems the I2C communication isn't working properly. https://github.com/bdeloeste/Nexys-4-Temperature-Sensor--ADT-7420/blob/master/VGA%20Module/vga_t emp_sensor.srcs/sources_1/new/I2C_temp.v this my constraint file ===================================> ## clock set_property -dict { PACKAGE_PIN E3 IOSTAN

## CRC is an FPGA PITA

inI had a newbie working on a bit wise CRC32 implementation and he could not = get the results of any of the many online CRC32 generators...

I had a newbie working on a bit wise CRC32 implementation and he could not = get the results of any of the many online CRC32 generators available. So I= coded up the same algorithm and tried it myself with similar results. =20 I tried digging around and found little that I could use to either evaluate= an algorithm or to generate comparison data other than the final result. = What I nee...

## Why am I getting different results with two files collapsed into one?

inI wrote a Verilog file: [code] // (c) 2020 Kevin Simonson module equ2 ( output result , output nrOut , output xwOut , input leftOp ...

I wrote a Verilog file: [code] // (c) 2020 Kevin Simonson module equ2 ( output result , output nrOut , output xwOut , input leftOp , input rightOp); wire notRight, xorWeak; supply1 power; supply0 ground; nmos #(3) nRg( notRight, ground , rightOp); pmos #(3) pRg( notRight, power , rightOp); nmos #(3) nXor( xorWeak , notRight, leftOp ); pmos #(3) pXor( xorWeak , ...

## Synthesizable open FPGA cores

inHi Experts, I am looking for Synthesizable FPGA (Xilinx) SOC cores like RUSC-V etc ( more than 100K LUTs) for evaluating their timing...

Hi Experts, I am looking for Synthesizable FPGA (Xilinx) SOC cores like RUSC-V etc ( more than 100K LUTs) for evaluating their timing performance. Could you please point me to their repositories ? Best

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