To Reset or not to Reset, That is the Question!

Started by gnua...@gmail.com in comp.arch.fpga2 years ago 4 replies

Whether tis nobler to suffer the slings and arrows of outrageous judgement = or just add the pointless, incorrectly working async reset that...

Whether tis nobler to suffer the slings and arrows of outrageous judgement = or just add the pointless, incorrectly working async reset that every frigg= in' text book and every training example shows. =20 I'm on a project where we have no strong guidance and one member of the tea= m is the type who *knows* how to work a project and so has zero interest in= considering what others are doin...


Using DSP Units

Started by gnua...@gmail.com in comp.arch.fpga2 years ago 7 replies

I working with the Gowin GW1N devices and need to do some serious math. By= serious, I mean a number of calculations, not that they have to be...

I working with the Gowin GW1N devices and need to do some serious math. By= serious, I mean a number of calculations, not that they have to be fast. = In fact, I pretty much have all the time in the world relatively speaking. = The cycle time for performing all the calculations is 5 ms with a 33 MHz c= lock, so 167,000 odd cycles. =20 What I'm not up to speed about is just how to use or...


Programming a Traffic Light Controller In verilog using Quartus Prime Lite

Started by Dave Wood in comp.arch.fpga2 years ago 3 replies

Hi everyone, ( Don't know if this is even the right place to post a question but ill tr= y my luck) So basically I am a student and I have a...

Hi everyone, ( Don't know if this is even the right place to post a question but ill tr= y my luck) So basically I am a student and I have a final project to build a traffic l= ight control system using Verilog, and then I am to program my FPGA board w= hich is a De10-lite. I feel like the coding aspect of the project isn't bad= . I have cases and such set up to switch the device to differe...


ADCs in FPGAs

Started by Rick C in comp.arch.fpga2 years ago 23 replies

I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all digitally, or almost so. I'm...

I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all digitally, or almost so. I'm not completely clear on how to do it. Lattice has a reference design using an LVDS receiver as a comparator. They use an RC filter on the output bit as the reference voltage for the input. I'm having trouble relating this to the typ


Is there a way in Verilog to refer to a slice of an array?

Started by Kevin Simonson in comp.arch.fpga2 years ago 9 replies

I've got two Verilog modules that look like this: module queue ( output [ 64:0] dataOut , input reset , input ...

I've got two Verilog modules that look like this: module queue ( output [ 64:0] dataOut , input reset , input shift , input [ 64:0] dataIn); ... endmodule and module lessThan ( output lssThn , input [ 48:0] leftOp , input [ 48:0] rightOp); ... endmodule I've got six instances of module (queue) and need to pipe the forty-nine mo= st si...


Finally! I figgured it out accidentally.

Started by Rick C in comp.arch.fpga2 years ago 2 replies

Sometimes the tools are hard to figure out. I've been looking for a way to leave my source files in MY source directory rather than in the...

Sometimes the tools are hard to figure out. I've been looking for a way to leave my source files in MY source directory rather than in the Active-HDL source directory buried down in the bowels of their extraneous files directories. I was having a problem with the tool that i think is going to require rebooting the machine and rather than do that I'm working around not being abl


Is there a way in Verilog to refer to a slice of an array?

Started by Kevin Simonson in comp.arch.fpga2 years ago

I've got two Verilog modules that look like this: module queue ( output [ 64:0] dataOut , input reset , input ...

I've got two Verilog modules that look like this: module queue ( output [ 64:0] dataOut , input reset , input shift , input [ 64:0] dataIn); ... endmodule and module lessThan ( output lssThn , input [ 48:0] leftOp , input [ 48:0] rightOp); ... endmodule I've got six instances of module (queue) and need to pipe the forty-nine mo= st si...


HP "owning" the software for Xilinx-FTDI drivers???

Started by Rick C in comp.arch.fpga2 years ago 6 replies

Someone new on the project is talking about how HP owns the driver code for= the FTDI JTAG chip used to program Xilinx parts. Has anyone heard...

Someone new on the project is talking about how HP owns the driver code for= the FTDI JTAG chip used to program Xilinx parts. Has anyone heard of this= ? =20 Even if that is true, I'm not sure how relevant it is. Is there some issue= with HP owning the software for FTDI devices even if that is true? Why wo= uld it matter to a user of Xilinx FPGAs??? I did try getting an answer and f...


ready/valid vs 2-way handshaking vs 4-way handshaking

Started by Ubaid Abdullah in comp.arch.fpga2 years ago 4 replies

I am confused about whether ready/valid handshaking is functionally equival= ent to req/ack (2-way) handshaking? By being functionally...

I am confused about whether ready/valid handshaking is functionally equival= ent to req/ack (2-way) handshaking? By being functionally equivalent, I mea= n that we can perform data transfers with ready/valid handshaking in all th= e cases in which we can do with req/ack (2-way) handshaking and vice versa?= Are there any scenarios in which one scheme will work while the other will= not? A...


Active-HDL Throws Error

Started by Rick C in comp.arch.fpga2 years ago 14 replies

My code is assigning an incremented unsigned value to an aggregate so the s= um and carry can be extracted without duplicating logic or excessive...

My code is assigning an incremented unsigned value to an aggregate so the s= um and carry can be extracted without duplicating logic or excessive lines = of code (VHDL can be verbose we all know). But it seems this one usage mak= es the Active-HDL simulator complain. I'm adding an integer 1 to the unsig= ned counter value after being resized to be 1 bit larger to match the left = hand side ...


Ask a Question to the FPGARelated community

To significantly increase your chances of receiving answers, please make sure to:

  1. Use a meaningful title
  2. Express your question clearly and well
  3. Do not use this forum to promote your product, service or business
  4. Write in clear, grammatical, correctly-spelled language
  5. Do not post content that violates a copyright