How to generate bits info for a record structure?

Started by Weng Tianxiang in comp.arch.fpga1 year ago 9 replies

Hi, I have a data record designed as follows: type DATA_RECORD_t record I1: unsigned(7 downto 0); I2: unsigned(15 downto 0); end...

Hi, I have a data record designed as follows: type DATA_RECORD_t record I1: unsigned(7 downto 0); I2: unsigned(15 downto 0); end record; I want to get its bit number and don't want to manually calculate the bit number. How can I do it? Thank you. Weng


how to suppress assertion warnings in gtkwave?

Started by the clever Bit in comp.arch.fpga1 year ago 3 replies

hello, is there any way to suppress assertion warnings from std.numeric in gtkwave simulator? thank you

hello, is there any way to suppress assertion warnings from std.numeric in gtkwave simulator? thank you


Apple eBook on Educational CPU design using FPGA

Started by Othman Ahmad in comp.arch.fpga1 year ago

https://books.apple.com/us/book/implementing-a-cpu-using-fpga/id802454238

https://books.apple.com/us/book/implementing-a-cpu-using-fpga/id802454238


Displays - Apple Mac vs. IBM PC

Started by Rick C in comp.arch.fpga1 year ago 10 replies

I bet the Apple still have a huge leg up on PCs when it comes to displays. Yeah, they both have the same hardware these days, but the way the...

I bet the Apple still have a huge leg up on PCs when it comes to displays. Yeah, they both have the same hardware these days, but the way the software manages things is so much better on the Mac. I remember using a Mac many years ago and everything from top to bottom had a consistent look and feel. On the PC every program is in it's own world with unique fonts, sizes and windows.


Optimizations, How Much and When?

Started by Rick C in comp.arch.fpga1 year ago 11 replies

My projects typically are implemented in small devices and so are often space constrained. So I am in the habit of optimizing my code for...

My projects typically are implemented in small devices and so are often space constrained. So I am in the habit of optimizing my code for implemented size. I've learned techniques that minimize size and tend to use them everywhere rather than the 20/80 rule of optimizing the 20% of the code where you get 80% of the benefit, or 10/90 or whatever your favorite numbers are. I


Can't get image from PCam 5C running on Zybo Z7-20 with petalinux

Started by Swapnil Patil in comp.arch.fpga1 year ago

Hello folks, I am running Zybo Z7-20 Pcam petalinux project on Zybo Z7-20 board. From README.md file below command will create 14 image...

Hello folks, I am running Zybo Z7-20 Pcam petalinux project on Zybo Z7-20 board. From README.md file below command will create 14 image files in current directory yavta -c14 -f YUYV -s "$width"x"$height" -F /dev/video0 when we test similarly our log stucks as per below root@test0:~# yavta -c1 -f YUYV -s "$width"x"$height" -F /dev/video0 Device /dev/video0 opened. Device `video_...


Efinix and their new Trion FPGAs -

Started by Brane2 in comp.arch.fpga1 year ago 10 replies

I'm talking about these guys: https://www.efinixinc.com Their Trion program seems interesting: - it stretches from area that is occupied...

I'm talking about these guys: https://www.efinixinc.com Their Trion program seems interesting: - it stretches from area that is occupied by Lattice's MachXO3 on the low end and ECP5 on hight end - no onboard FLASH.Just OTP on few small models and nothing on high end - universal tile that can do routing as well as LUT/MEM/logic - 5 bit BLOCK RAM instead of traditional 9-bit - additiona...


Enabler for New FPGA Companies

Started by Rick C in comp.arch.fpga1 year ago 2 replies

There seem to be a spate of new FPGA companies coming out. The road block to new FPGA companies has always been two things, patents and...

There seem to be a spate of new FPGA companies coming out. The road block to new FPGA companies has always been two things, patents and software... and maybe software patents. lol So what has changed? For sure FPGAs have been around long enough that many of the basic patents have expired. The LUT/FF combo that is the basis for all FPGAs has been available for some time


Anybody used Amazon AWS for HW sims?

Started by Kevin Neilson in comp.arch.fpga1 year ago 4 replies

Has anybody used Amazon AWS for FPGA hardware sims? I don't know anything about it and I tried to read up on it but it's all a bit vague. Amazon...

Has anybody used Amazon AWS for FPGA hardware sims? I don't know anything about it and I tried to read up on it but it's all a bit vague. Amazon has farms of FPGAs (Xilinx, I think?) but they mostly market these as software accelerators, meant to be somewhat abstracted from most users. But I'm wondering if I can upload bitfiles and do hardware sims. For example, to characterize


New coding method for a state machine in groups in HDL

Started by Weng Tianxiang in comp.arch.fpga1 year ago 33 replies

Hi everyone, Welcome all critics from ones who are interested in coding state machine that seems to many as matured, but can be further...

Hi everyone, Welcome all critics from ones who are interested in coding state machine that seems to many as matured, but can be further improved. Here is a coding snippet for new method you can immediately understand what will happening for coding a state machine. type State_Machine_t is ( First_group : (s1, s2, s3), Second_Group : (s4, s5, s6), Third_Group ; (s7, s8, s9) ); s...


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