VHDL or Verilog?

Started by Rick C. Hodgin in comp.arch.fpga11 months ago 20 replies

I've been given conflicting device on which language to use. There are people I would consider to be expert professionals who tell me to use...

I've been given conflicting device on which language to use. There are people I would consider to be expert professionals who tell me to use VHDL, and others who tell me Verilog. Most everybody tells me that if I use VHDL there's less chance for error, but that it does take more effort to learn. Any thoughts? Thank you, Rick C. Hodgin


Create FPGA to replace 1974 MOSTEK MK5017

Started by Anonymous in comp.arch.fpga11 months ago 3 replies

Hi Everyone, Perhaps you may have a skill to create FPGA and create a clone for 1974 MOSTEK MK5017, famous clock chip by Heathkit. They used...

Hi Everyone, Perhaps you may have a skill to create FPGA and create a clone for 1974 MOSTEK MK5017, famous clock chip by Heathkit. They used this chip on model GC-1005 and run with Panaplex display tubes by Sperry Rand. Unfortunately, MOSTEK went out of business (thanks to US EPA that destroyed wonderful company by enormous fines instead of help to clean). Nowdays, it is impossib


Whups. Lattice Diamond says my package does not exist.

Started by Anonymous in comp.arch.fpga11 months ago 5 replies

Hi all. I'm stopped. Lattice Diamond does not offer a configuration for designing with my part in the 48-VFQFN package. The LCMXO2-640HC-6SG48I...

Hi all. I'm stopped. Lattice Diamond does not offer a configuration for designing with my part in the 48-VFQFN package. The LCMXO2-640HC-6SG48I is not available in the drop-down configuration menu. They say the closest they can get is the TQFP-100 or CSBGA-132 packages. My PCB and FPGA arrived days ago but I need a way to do development! Is there a way to configure Lattice Diamond


ZAP : An open source ARM processor (feedback)

Started by Anonymous in comp.arch.fpga12 months ago 19 replies

Hi, I am the author of the Gihub project ZAP ( https://github.com/krevanth/ZAP ). It is a 10-stage pipelined ARMv4T compatible soft processor...

Hi, I am the author of the Gihub project ZAP ( https://github.com/krevanth/ZAP ). It is a 10-stage pipelined ARMv4T compatible soft processor core with cache and memory management support. I developed it during my final semester in university. Would like your feedback/criticism of the project. Thanks, K Revanth


baud_generator (16x baud) used in UART transmitter logic

Started by _Xilinx in comp.arch.fpga12 months ago 3 replies

For http://www.ti.com/lit/ds/symlink/pc16550d.pdf#page=17 , how is the output of baud_generator (16x baud) used in transmitter logic ? I only...

For http://www.ti.com/lit/ds/symlink/pc16550d.pdf#page=17 , how is the output of baud_generator (16x baud) used in transmitter logic ? I only see there is a transmitter timing control block in the functional block diagram, but I am not sure how it works exactly. Anyone ?


fpga zigbee interface

Started by Anonymous in comp.arch.fpga1 year ago 2 replies

i have spartan6 atlys(LX45) board, can anyone suggest me how to interface zigbee to this board to communicate with pc.thnx

i have spartan6 atlys(LX45) board, can anyone suggest me how to interface zigbee to this board to communicate with pc.thnx


Accelerating Face Detection on Zynq-7020 Using High Level Synthesis

Started by yuning he in comp.arch.fpga1 year ago 6 replies

Hello, here is my question: Purpose: realize face detection on zynq-7020 SoC Platform: Zedboard with OV5640 camera Completed work: capturing...

Hello, here is my question: Purpose: realize face detection on zynq-7020 SoC Platform: Zedboard with OV5640 camera Completed work: capturing video from camera, writing into DDR for storage and reading from DDR for display Question: how to realize a face detection IP and its throughput can reach 30fps(pixel 320*240) Here are my jobs: Base on the Viola Jones algorithm, using HLS(high level ...


Spartan 6 Digital controlled oscillator

Started by john tra in comp.arch.fpga1 year ago 2 replies

Hello, What is the best way to implement a 30 MHz clock generation circuit that can be dynamically controlled to provide fine frequency...

Hello, What is the best way to implement a 30 MHz clock generation circuit that can be dynamically controlled to provide fine frequency offsets in a Spartan 6, the clock is to be used internally and output via a pin? Would a DCM provide the functionality and what would the minimum frequency increment be? Thanks John


Configuration fault recovery

Started by Yannick Lamarre in comp.arch.fpga1 year ago 4 replies

Hi all, I've been thinking about this problem for a while and shared it with a few colleagues, but no one has yet to come up with an answer. For...

Hi all, I've been thinking about this problem for a while and shared it with a few colleagues, but no one has yet to come up with an answer. For some configuration, an FPGA can be configured so that two different drivers are connected on that same line internally. A practical example would be two BUFGs driving the same line on a Spartan6. If those two drivers are driving a different value in a ...


Pipelining on Multiple Clock Edges

Started by rickman in comp.arch.fpga1 year ago 8 replies

I recall a processor implementation where the guy tried to say that one particular part of the pipeline design had a register inserted which was...

I recall a processor implementation where the guy tried to say that one particular part of the pipeline design had a register inserted which was clocked on the negative edge. I could never see how this would positively impact anything. In fact, the setup and hold time of the register, not to mention the routing time, would add to the delay in that pipeline stage. Was I missing somet...


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