increment or decrement one of 16, 16-bit registers

Started by Tim Wescott in comp.arch.fpga4 months ago 22 replies

I've been geeking out on the COSMAC 1802 lately -- it was the first processor that I owned all just for me, and that I wrote programs for (in...

I've been geeking out on the COSMAC 1802 lately -- it was the first processor that I owned all just for me, and that I wrote programs for (in machine code -- not assembly). One of the features of this chip is that while the usual ALU is 8-bit and centered around memory fetches and the accumulator (which they call the 'D' register), there's a 16 x 16-bit register file. Any one of these ...


size lattice iCE40 config files

Started by kristoff in comp.arch.fpga4 months ago 2 replies

Hi all, I am working on a STM32-based programmer for the olimex iCE40HX1K-EVB fpga dev.board. (now trying to implement the "SPI Slave...

Hi all, I am working on a STM32-based programmer for the olimex iCE40HX1K-EVB fpga dev.board. (now trying to implement the "SPI Slave configuration" protocol). Looking at the Lattice "programming and Configuration guide" (page 11), it is noted on table 8 that a FLASH EPROM for a ICE40-LP/LX1K must be at least 34112 bytes. However, all binary-files as created by the icestorm-tools...


Lattice iCE40 UltraLite DIPSY - what happened?

Started by rickman in comp.arch.fpga4 months ago 6 replies

I was digging around for info on the iCE40 UL and found info on the DIPSY from 2015 when it was breaking news. Not sure how I missed it, but...

I was digging around for info on the iCE40 UL and found info on the DIPSY from 2015 when it was breaking news. Not sure how I missed it, but this is a very small unit with a very tiny FPGA (likely the smallest FPGA package ever - 2 mm^2) and an LDO for the core power and of course some connectors. I found a github page with various design details and an Indiegogo page. There I foun...


glitching AND gate

Started by David Bridgham in comp.arch.fpga4 months ago 25 replies

I have a question about how FPGAs handle signals into combinational logic. I have following setup: always @(posedge interrupt_check)...

I have a question about how FPGAs handle signals into combinational logic. I have following setup: always @(posedge interrupt_check) interrupt_detect


RISC-V Support in FPGA

Started by rickman in comp.arch.fpga4 months ago 62 replies

I don't recall where, but there was a conversation recently about using the RISC-V in FPGAs. Thought I'd pass on the...

I don't recall where, but there was a conversation recently about using the RISC-V in FPGAs. Thought I'd pass on the link. https://www.microsemi.com/products/fpga-soc/technology-solutions/embedded-processing/risc-v -- Rick C


Lattice ECP5 succesor ( with DDR4 phy) ?

Started by Brane2 in comp.arch.fpga4 months ago 4 replies

AFAIK ECP5 is good for interfacing with DDR3, but not DDR4. Is there a plan to introduce new members with DDR4 or perhaps new family with such...

AFAIK ECP5 is good for interfacing with DDR3, but not DDR4. Is there a plan to introduce new members with DDR4 or perhaps new family with such interface ?


POLL: Would you want to know?

Started by Rick C. Hodgin in comp.arch.fpga4 months ago 30 replies

I have said previously I would not post in this group about Jesus any longer. But I fear I have sinned against God in making that statement. ...

I have said previously I would not post in this group about Jesus any longer. But I fear I have sinned against God in making that statement. So, I want to ask a poll: Question: If you were wrong in your belief that we do not need Jesus to forgive us of sin ... would you want to know? Please answer yes or no: Yes -- You WOULD want to know if you were wrong. ...


When I'm Wrong I'd Like to Know

Started by rickman in comp.arch.fpga4 months ago 1 reply

But each topic I'm wrong about should be addressed in that newsgroup. If I were wrong about something related to FPGAs (just an imaginary...

But each topic I'm wrong about should be addressed in that newsgroup. If I were wrong about something related to FPGAs (just an imaginary example, of course) I wouldn't want it discussed in alt.religion.emacs. Likewise I don't wish for things not related to FPGAs to be discussed here. Every discussion in its place! Is there any chance the person this post is directed to will actually ...


creating a seed on a FPGA.

Started by kristoff in comp.arch.fpga5 months ago 6 replies

Hi, I am aware that the best way to create a seed (for random numbers) is external hardware, but does anybody know any cheap-and-easy tricks...

Hi, I am aware that the best way to create a seed (for random numbers) is external hardware, but does anybody know any cheap-and-easy tricks to generate a random-ish number on an FPGA. Kristoff


Cyclotomic FFTs

Started by Kevin Neilson in comp.arch.fpga5 months ago

I've been researching cyclotomic FFTs. There is a lot of literature (Fedorenko, Trifinov, Costa, etc.) about using this technique for calculating...

I've been researching cyclotomic FFTs. There is a lot of literature (Fedorenko, Trifinov, Costa, etc.) about using this technique for calculating the syndrome and doing the Chien Search in Reed-Solomon decoders. I'd like to know if anybody has actually used this in hardware. The literature makes bold claims about the massive 100x efficiency gains, but it seems like it's only usef


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