handshacking between modules, best practices ?

Started by kristoff in comp.arch.fpga8 months ago 6 replies

Hi, Last weekend, I was continueing on my small project to use a FPGA as DAC. I now use a hardware DAC (tlc5615). So I have two...

Hi, Last weekend, I was continueing on my small project to use a FPGA as DAC. I now use a hardware DAC (tlc5615). So I have two modules, a top-level module for the DDS and an additional module to drive the TLC. I have two signal for handshacking ("load" and "done"). At a certain point, I had the problem that one of the signals wasn't dropped fast enough, which resulted in a weir...


Simulation of PCIe at TLP level

Started by Svenn Are Bjerkem in comp.arch.fpga8 months ago 1 reply

Hi, has anybody simulated PCIe at TLP level? I would like to feed a 1x PCIe endpoint interface with data as if it was inserted into a host PCIe...

Hi, has anybody simulated PCIe at TLP level? I would like to feed a 1x PCIe endpoint interface with data as if it was inserted into a host PCIe slot. I need some pointers to documents or code describing what I have to do to make a simplem memory read and memory write. -- Svenn


Xilinx Virtex4 Outputs for Camera Link

Started by Brad Smallridge in comp.arch.fpga8 months ago 18 replies

Can anyone tell me what I need to drive a Camera Link output directly from a V4? I have tried LVCMOS25 and I can see differential signals at the...

Can anyone tell me what I need to drive a Camera Link output directly from a V4? I have tried LVCMOS25 and I can see differential signals at the outputs but at the end of a 2 meter cable I see only DC differential levels as if the signals are dampened somehow. Brad Smallridge aivision


FPGA LABVIEW programming

Started by john in comp.arch.fpga8 months ago 9 replies

Hello, National instruments has introduced new module in their labview 8 for programming the xilinx FPGA chips. It converts the labview...

Hello, National instruments has introduced new module in their labview 8 for programming the xilinx FPGA chips. It converts the labview programs into VHDL . It can borrow image processing libraries from the labview too. I was wondering that if somebody has used this module form labview can give me details about it. Thanks Regards John


Lattice Semiconductor XP2 Brevia 2 help on keyboard controller

Started by Rick C. Hodgin in comp.arch.fpga8 months ago 3 replies

I have an IBM Model-F capacitive keyboard. I would like to design my own keyboard controller for it. I understand logically how to do it, but...

I have an IBM Model-F capacitive keyboard. I would like to design my own keyboard controller for it. I understand logically how to do it, but I need help with the mechanics. Would somebody be interested in helping me? I have a mod which makes the layout more like traditional keyboards, except I replaced the single enter key on the numpad with two keys as there were capacitive sensors t...


Analog to digital converters

Started by Rick C. Hodgin in comp.arch.fpga8 months ago 10 replies

I don't know where to ask this, so I'll try here. Are analog to digital converters fundamentally, in their core inner design, basically tiny...

I don't know where to ask this, so I'll try here. Are analog to digital converters fundamentally, in their core inner design, basically tiny systems which operate like 555 timers, with a series of resistors and capacitors designed to sample ranges, essentially counting ticks per fixed units of time, resulting in the digital data necessary to perform an indexed lookup from the inner sampler ...


designing a fpga

Started by kristoff in comp.arch.fpga8 months ago 38 replies

Hi all, A couple of weeks ago, I was watching the talk of Wolf Clifford on his opensource fpga flow at...

Hi all, A couple of weeks ago, I was watching the talk of Wolf Clifford on his opensource fpga flow at ccc. (https://www.youtube.com/watch?v=SOn0g3k0FlE) At the end, he mentions designing an open-source fpga and the replies he got when he mentioned the idea to hardware-companies. Appart from the question about the usefullness or economic viability of the idea itself (1), it did ge...


temperature sense diodes in Xilinx 7 series

Started by John Larkin in comp.arch.fpga8 months ago 6 replies

Has anybody used these? We have two FPGAs on a board, a Zynq and an Artix7. We want to use the internal ADCs to read chip temperatures. We...

Has anybody used these? We have two FPGAs on a board, a Zynq and an Artix7. We want to use the internal ADCs to read chip temperatures. We have been advised to ground the temp sense diode pins DXP and DXN "if they are not being used". Unless the XADC has a separate temp sense diode, seems to me that shorting the external diode pins might kill our ability to acquire temperature internall...


Two good FREE e-books about Ireland

Started by Anonymous in comp.arch.fpga9 months ago

http://www.rbduncan.com/Sean.htm http://www.rbduncan.com/TheTroubles.htm

http://www.rbduncan.com/Sean.htm http://www.rbduncan.com/TheTroubles.htm


The TOP Rule

Started by Anonymous in comp.arch.fpga9 months ago 2 replies

http://www.rbduncan.com/toprule.htm

http://www.rbduncan.com/toprule.htm


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