I've got two Verilog modules that look like this: module queue ( output [ 64:0] dataOut , input reset , input ...

I've got two Verilog modules that look like this: module queue ( output [ 64:0] dataOut , input reset , input shift , input [ 64:0] dataIn); ... endmodule and module lessThan ( output lssThn , input [ 48:0] leftOp , input [ 48:0] rightOp); ... endmodule I've got six instances of module (queue) and need to pipe the forty-nine mo= st si...

Sometimes the tools are hard to figure out. I've been looking for a way to leave my source files in MY source directory rather than in the...

Sometimes the tools are hard to figure out. I've been looking for a way to leave my source files in MY source directory rather than in the Active-HDL source directory buried down in the bowels of their extraneous files directories. I was having a problem with the tool that i think is going to require rebooting the machine and rather than do that I'm working around not being abl

I've got two Verilog modules that look like this: module queue ( output [ 64:0] dataOut , input reset , input ...

I've got two Verilog modules that look like this: module queue ( output [ 64:0] dataOut , input reset , input shift , input [ 64:0] dataIn); ... endmodule and module lessThan ( output lssThn , input [ 48:0] leftOp , input [ 48:0] rightOp); ... endmodule I've got six instances of module (queue) and need to pipe the forty-nine mo= st si...

Someone new on the project is talking about how HP owns the driver code for= the FTDI JTAG chip used to program Xilinx parts. Has anyone heard...

Someone new on the project is talking about how HP owns the driver code for= the FTDI JTAG chip used to program Xilinx parts. Has anyone heard of this= ? =20 Even if that is true, I'm not sure how relevant it is. Is there some issue= with HP owning the software for FTDI devices even if that is true? Why wo= uld it matter to a user of Xilinx FPGAs??? I did try getting an answer and f...

I am confused about whether ready/valid handshaking is functionally equival= ent to req/ack (2-way) handshaking? By being functionally...

I am confused about whether ready/valid handshaking is functionally equival= ent to req/ack (2-way) handshaking? By being functionally equivalent, I mea= n that we can perform data transfers with ready/valid handshaking in all th= e cases in which we can do with req/ack (2-way) handshaking and vice versa?= Are there any scenarios in which one scheme will work while the other will= not? A...

My code is assigning an incremented unsigned value to an aggregate so the s= um and carry can be extracted without duplicating logic or excessive...

My code is assigning an incremented unsigned value to an aggregate so the s= um and carry can be extracted without duplicating logic or excessive lines = of code (VHDL can be verbose we all know). But it seems this one usage mak= es the Active-HDL simulator complain. I'm adding an integer 1 to the unsig= ned counter value after being resized to be 1 bit larger to match the left = hand side ...

Just had my first taste of the company supplied software from Gowin Semicon= ductor. It's ok. Documentation is terrible being not much more...

Just had my first taste of the company supplied software from Gowin Semicon= ductor. It's ok. Documentation is terrible being not much more than a lis= ting of the menu items. Lots of features are lacking.=20 My test file is a simple 11 bit down counter described three slightly diffe= rent ways to see what might be the best for my current design which is goin= g to have a lot of counters...

One of my guys is suggesting that we ground unused balls on an FPGA and compile them to be low outputs, the idea being to reduce...

One of my guys is suggesting that we ground unused balls on an FPGA and compile them to be low outputs, the idea being to reduce ground impedance and add some damping. Has anyone done this? Does it help? I guess I could have an input that controls the tri-states of all such pins, and also bring out one logic-low to scope, and turn the grounds on and off and see if it makes any difference...

I recently posted a Verilog module to this forum, and someone responded that I was coding at a very low level, which was true; I was referring to...

I recently posted a Verilog module to this forum, and someone responded that I was coding at a very low level, which was true; I was referring to XOR gates, NAND gates, NOR gates, and NOT gates. Is there something wrong with writing my code at such a low level? If I have a fairly good understanding of how my algorithm needs to run at such a low level, then what is wrong with writing

I'm reading reports that AMD is working on buying Xilinx and Qualcom and Broadcom may make bids as well. Stock is up from last week's close of...

I'm reading reports that AMD is working on buying Xilinx and Qualcom and Broadcom may make bids as well. Stock is up from last week's close of $105.99. Other than the company name on documentation I've seen little sign that the Intel purchase of Altera has impacted operations. I wonder if the same can be said for an AMD purchase of Xilinx, or Broadcom or Qualcom. -- Rick C. -...