MPMC simulation

Started by Saylee in comp.arch.fpga6 years ago

Hi, I am simulating MPMC with Isim version 12.4. I have written a test bench to give inputs to microblaze instance. Here i am facing...

Hi, I am simulating MPMC with Isim version 12.4. I have written a test bench to give inputs to microblaze instance. Here i am facing problem of MPMC simulation. The MPMC is not generating NPI output signals like MCB_DDR2_PIM1_InitDone_pin, MCB_DDR2_PIM1_WrFIFO_Empty_pin etc as required. Please help me in this problem. Thank you... -------------------------------------...


Problem in simulating Xilinx MPMC in VCSMX

Started by Anonymous in comp.arch.fpga9 years ago

Hi, I have been trying to simulate Xilinx's MPMC (mpmc_v4_02_a, a DDR memory controller) in VCSMX. But it is not working. i.e.,...

Hi, I have been trying to simulate Xilinx's MPMC (mpmc_v4_02_a, a DDR memory controller) in VCSMX. But it is not working. i.e., the MPMC_InitDone is at value '0' for some time then goes to 'z' indefinitely. But the same MPMC is working OK in Modelsim,. How to do the MPMC simulation work in VCSMX? Has anyone tried it before, successfully? Best regards, Muthu


MPMC and DDR2 Simulation

Started by simax in comp.arch.fpga9 years ago 3 replies

Hello Im trying to simulate the MPMC with an DDR2 Memory. Ive got the problem that the mpmc wont initialise the ddr2 modul....

Hello Im trying to simulate the MPMC with an DDR2 Memory. Ive got the problem that the mpmc wont initialise the ddr2 modul. The Idelayctrl_Rdy_I is 1 but it wont talk to the memory. Im using the mt47h64m16 memory modul from freemodelfoundry. My mpmc is instantiated with : BEGIN mpmc PARAMETER INSTANCE = mpmc_0 PARAMETER HW_VER = 4.03.a PARAMETER C_MEM_PARTNO = MT47H64M16-3 ...


MPMC does not finish initialization in simulation

Started by shubhendu in comp.arch.fpga5 years ago 2 replies

Hello Friends, I am working on virtex6. I am trying to debug a problem by simulating in modelsim. But in the simulation I get a different...

Hello Friends, I am working on virtex6. I am trying to debug a problem by simulating in modelsim. But in the simulation I get a different problem. My platform uses DDR3 SDRAM via xilinx's MPMC (6.02a). During simulation, the MPMC gets busy initializing itself, but never finishes (at least not for until 2ms). To fasten the initialization in the MHS file, I first set PARAMETER C_SKIP_S...


Problem with mpmc(4.02.a) simulation -- DDR never initializes

Started by rao in comp.arch.fpga9 years ago 5 replies

Hi, I am trying to simulate a EDK system based on microblaze. I have 10 slaves and one of the slave is a mpmc(4.02.a) and has ...

Hi, I am trying to simulate a EDK system based on microblaze. I have 10 slaves and one of the slave is a mpmc(4.02.a) and has microblaze i/d cache connections on 2 ports and a external DDR interface on third port. I have a simple program that performs read and write to register bits in each of the slaves. All the slaves on the bus are responding except mpmc. When I tried to...


MPMC without MCB on Spartan-6

Started by Sebastien Matel in comp.arch.fpga7 years ago 2 replies

Hi, Is there a way to hack the MPMC into not using the MCB (but the softcore MIG) on Spartan-6? The MPMC datasheet says no, but since the MIG...

Hi, Is there a way to hack the MPMC into not using the MCB (but the softcore MIG) on Spartan-6? The MPMC datasheet says no, but since the MIG source code is mostly behavioral (iirc), maybe there is a way around this. I have a board with DDR SDRAM and a pinout that is not compatible with the MCB, and my custom softcore platform (that is not using the MCB) randomly crashes when running co...


using mpmc ddr2 controller with an other processor

Started by rpon...@gmail.com in comp.arch.fpga9 years ago 1 reply

hi groups ! what is the best route in order to use an edk generated mpmc ddr2 controller with a custom processor (not microblaze, but gaisler...

hi groups ! what is the best route in order to use an edk generated mpmc ddr2 controller with a custom processor (not microblaze, but gaisler leon3 or even picoblaze ; this is for edu. purpose...) ? I have a copy the ddr2_sdram_wrapper.ngc and clock_generator_0_wrapper.ngc files (these are good, tested with a microblaze design). I read xilinx mpmc.pdf but I am lost ... I think I need ...


using hard tri-mode ethernet MAC and MPMC on virtex 5

Started by Anonymous in comp.arch.fpga9 years ago 5 replies

Hi, does anybody have any experience in using Virtex 5 FPGA with 1) MPMC 2) tr-mode ethernet MAC hard core with the xps_ll_temac and...

Hi, does anybody have any experience in using Virtex 5 FPGA with 1) MPMC 2) tr-mode ethernet MAC hard core with the xps_ll_temac and the ll_fifo? The card I am working on has an input of 100 MHz. this is the problem that I face, something which i am not sure: 1) MPMC has to run at a multiple of 133 MHz etc...thus the whole microblaze PLB system has to run at 133 MHz? 2) the xps_l...


MPMC On EDK

Started by ratemonotonic in comp.arch.fpga10 years ago 4 replies

Hi All , I am trying to interface microblaze with a Micron DDR SDRAM (MT46V16M16FG-75 16Mx16) using MPMC from the IP catalogue. As I...

Hi All , I am trying to interface microblaze with a Micron DDR SDRAM (MT46V16M16FG-75 16Mx16) using MPMC from the IP catalogue. As I am running on Spartan 3 FPGA I need to connect port lines - DDR_DQS_DIV_O and DDR_DQS_DIV_I , else I get errors , it also states that these should be connected in for spartan 3. The problem is that there is not much documentation about these port lines in ...


Xilinx ISE 10.1 SP3 MPMC NPI VHDL simple sample needed

Started by Anonymous in comp.arch.fpga9 years ago 3 replies

Hello all, as a newbe with FPGAs I have no clue how to use the NPI interface of the MPMC from Xilinx. I haven't found a really good...

Hello all, as a newbe with FPGAs I have no clue how to use the NPI interface of the MPMC from Xilinx. I haven't found a really good example. What I need is a simple module in VHDL which reads and writes the memory (maybe a simple memory test). Is there something available ??? Can someone help me out ? Thanks a lot! /HB


Xilinx GbE performance

Started by Antti in comp.arch.fpga8 years ago 2 replies

Hi does anybody have real and realistic performance figures for Xilinx GbE solution with XPS_TEMAC/MPMC ? we need to get 60% of GbE...

Hi does anybody have real and realistic performance figures for Xilinx GbE solution with XPS_TEMAC/MPMC ? we need to get 60% of GbE wirespeed, UDP transmit only but it seems like real hard target to reach :( MPMC has memory latency of 23 cycles (added to EACH memory access cycle) so the ethernet SDMA takes a lot of bandwith already, there is another DMA writing data at same speed, an...


Re: Xilinx GbE performance

Started by Jan Pech in comp.arch.fpga8 years ago 11 replies

On Tue, 2009-06-02 at 09:53 -0700, Antti wrote: > Hi > > does anybody have real and realistic performance figures for Xilinx > GbE...

On Tue, 2009-06-02 at 09:53 -0700, Antti wrote: > Hi > > does anybody have real and realistic performance figures for Xilinx > GbE solution with XPS_TEMAC/MPMC ? > > we need to get 60% of GbE wirespeed, UDP transmit only but it seems > like real hard target to reach :( > > MPMC has memory latency of 23 cycles (added to EACH memory access > cycle) so the ethernet > SDMA takes a lot


Xilinx EDK 10.1 - SDRAM access using MPMC/VFBC by peripheral

Started by Anonymous in comp.arch.fpga8 years ago 1 reply

Hello all, i try to make an accelerator that will share the SDRAM with Microblaze using a VFBC port on the MPMC. I use the Spartan 3E...

Hello all, i try to make an accelerator that will share the SDRAM with Microblaze using a VFBC port on the MPMC. I use the Spartan 3E Starter Kit and XPS 10.1. So, I created a core with the wizard, it has a FSL bus and I also created a VFBC bus too. For the first test, I try to write 32 bytes to the SDRAM when the processor sends a "1" through the FSL and verify the operation by reading...


Periodic reads - Xilinx Virtex6

Started by zwalter in comp.arch.fpga5 years ago

Hello! I read that the MPMC memory controller sends automaticly (1us period) periodic read request to the DDR3 module to measure the phase...

Hello! I read that the MPMC memory controller sends automaticly (1us period) periodic read request to the DDR3 module to measure the phase detection. (http://www.xilinx.com/support/answers/36719.htm -> Disabling Periodic Reads During Writes) I don't understand, that if the module is red in every 1us, than why is a refresh logic implemented in the mpmc module? I think with every read the cont


Microblaze and DDR2

Started by maxascent in comp.arch.fpga7 years ago 1 reply

Is it possible to interface DDR2 memory to a Microblaze processor by not using the MPMC. I have my own DDR controller that I want to...

Is it possible to interface DDR2 memory to a Microblaze processor by not using the MPMC. I have my own DDR controller that I want to use. Cheers Jon --------------------------------------- Posted through http://www.FPGARelated.com


Has anyone gotten the GSRD to run from Ace CF?

Started by Dave H in comp.arch.fpga11 years ago

I can build other designs and have them work using the ACE CF, however the GSRD does not seem to kick off the software application. I'm...

I can build other designs and have them work using the ACE CF, however the GSRD does not seem to kick off the software application. I'm very frustrated - is there an issue loading the external ddram through the mpmc? I'm using gsrd v7.1 w/edk 7.1 Any ideas?


MPMC4.03 DDR1 question

Started by MM in comp.arch.fpga8 years ago 2 replies

Does anyone know if I can run DDR1 type of memory at double the frequency of MPMC4.03 (EDK10.1) main clock? Or is this possible for DDR2 only? I...

Does anyone know if I can run DDR1 type of memory at double the frequency of MPMC4.03 (EDK10.1) main clock? Or is this possible for DDR2 only? I am having difficult time trying to understand this from the datasheet. So, before digging into the MPMC source code I thought I would try asking... Thanks, /Mikhail


XUPV2P & xps_tft controller

Started by EFR in comp.arch.fpga9 years ago

Hello, we're using EDK version 10.1 (with SP3) and have found the xps_tft controller in the project IP catalog which we're trying to implement....

Hello, we're using EDK version 10.1 (with SP3) and have found the xps_tft controller in the project IP catalog which we're trying to implement. But we've run into some problems which we think is related to the DDR SDRAM because when using the MPMC IP we can't select the VFBC (Video frame buffer) option. Is there any information available on the xps tft controller or a tutorial on howto int...


Microblaze and DDR2

Started by maxascent in comp.arch.fpga7 years ago 2 replies

I am trying to integrate my own DDR2 controller into a Microblaze processor. I have created a board support package file with the ports defined...

I am trying to integrate my own DDR2 controller into a Microblaze processor. I have created a board support package file with the ports defined and have added an IOTYPE attribute of XIL_MEMORY_V1. However when I run the bsb it thinks that I want to use the Xilinx MPMC. Maybe I shouldnt be adding this attribute, but I need EDK to know that this is a memory controller so that it will let me change t...


Spartan-3E SDRAM interface

Started by Eric Smith in comp.arch.fpga9 years ago 2 replies

I'm starting a design with an XC3S500E-4PQG208C and a 4M*32 SDR SDRAM (Micron MT48LC4M32B2 or equivalent, TSOP package), using MicroBlaze with...

I'm starting a design with an XC3S500E-4PQG208C and a 4M*32 SDR SDRAM (Micron MT48LC4M32B2 or equivalent, TSOP package), using MicroBlaze with the MPMC memory controller. I'm concerned about signal integrity and SSOs. Being on a shoestring budget, I unfortunately don't have an IBIS simulator. If I put the TSOP very close to the FPGA (QFP), and keep the trace lengths short, is it plausib...