Spartan-3E SDRAM interface

Started by Eric Smith in comp.arch.fpga13 years ago 2 replies

I'm starting a design with an XC3S500E-4PQG208C and a 4M*32 SDR SDRAM (Micron MT48LC4M32B2 or equivalent, TSOP package), using MicroBlaze with...

I'm starting a design with an XC3S500E-4PQG208C and a 4M*32 SDR SDRAM (Micron MT48LC4M32B2 or equivalent, TSOP package), using MicroBlaze with the MPMC memory controller. I'm concerned about signal integrity and SSOs. Being on a shoestring budget, I unfortunately don't have an IBIS simulator. If I put the TSOP very close to the FPGA (QFP), and keep the trace lengths short, is it plausib...


arm cortex M0 ds and legacy spartan 3E 3A 3ADSP starter kits

Started by rp p in comp.arch.fpga9 years ago 1 reply

hi folks, I am investigating for edu. purposes arm cortex M0 "design start edition" in legacy spartan3E1600 or 3adsp1800. Labs can't afford...

hi folks, I am investigating for edu. purposes arm cortex M0 "design start edition" in legacy spartan3E1600 or 3adsp1800. Labs can't afford new boards this year... I am especially interrested in ddr ram / (arm) ahb-lite wrapping : mig/mpmc xilinx tools dont have wizard for that bus, it shoud be doable, but tricky... is there something freely available ?? regards


Microblaze and DDR2

Started by maxascent in comp.arch.fpga11 years ago 2 replies

I am trying to integrate my own DDR2 controller into a Microblaze processor. I have created a board support package file with the ports defined...

I am trying to integrate my own DDR2 controller into a Microblaze processor. I have created a board support package file with the ports defined and have added an IOTYPE attribute of XIL_MEMORY_V1. However when I run the bsb it thinks that I want to use the Xilinx MPMC. Maybe I shouldnt be adding this attribute, but I need EDK to know that this is a memory controller so that it will let me change t...


Ballpark PLB frequency

Started by Steve in comp.arch.fpga14 years ago 15 replies

Hi, I'm designing a platform on a Xilinx Virtex 4 FX60 chip and I am somewhat conerned at the capabilities of the PLB bus in the system....

Hi, I'm designing a platform on a Xilinx Virtex 4 FX60 chip and I am somewhat conerned at the capabilities of the PLB bus in the system. I require very high throughput and I'm conerned that the PLB will be the main bottle neck in the design. I have two approches, use the PLB for all traffic in the system, or offload some of that traffic to a dedicated interface on the MPMC IP that Xilinx p...


XPS MPMC

Started by ratemonotonic in comp.arch.fpga14 years ago 3 replies

Hi all , I have been stumped by xilinx tools again ! I have just baught a Evaluation board , whos supporting software , base system etc...

Hi all , I have been stumped by xilinx tools again ! I have just baught a Evaluation board , whos supporting software , base system etc where writen using EDK 8.1 using older IP cores. Now I am using EDK 9.2i and all the IP cores in the catalogue are new and not compatable with the microblaze version on the older base system that came with the eval board. Is there an easy way to reuse this...


ISE/EDK12.2 Translate fails with "NgdBuild:467 - output pad net 'Ddr_Ck_N_0_OBUF' has an illegal buffer" and similar messages.

Started by MM in comp.arch.fpga11 years ago 10 replies

The project has top level in ISE and it includes a PPC subsystem. The problem seems to be with the latest MPMC core, which, at least in DDR2...

The project has top level in ISE and it includes a PPC subsystem. The problem seems to be with the latest MPMC core, which, at least in DDR2 mode, instantiates IOs in the source code. There is a Xilinx Answer Record for this exact problem, but with regards to ISE11. However, the proposed solution doesn't work. Has anyone experienced this and found a workaround? The project was originall...


ddr2 controller for xilinx 1800a dsp starter kit

Started by rpon...@gmail.com in comp.arch.fpga13 years ago

Hi xilinx geeks, mig2.1 can generate a ddr2 controller only for 3400adsp starter kit. is there a fully tested design suitable for the...

Hi xilinx geeks, mig2.1 can generate a ddr2 controller only for 3400adsp starter kit. is there a fully tested design suitable for the 1800adsp starter kit available somewhere ? xilinx provides only an edk/mpmc controller in its references designs. thanks, raph


Re: Why the second flip-flop in Virtex-6?

Started by Jan Pech in comp.arch.fpga13 years ago 1 reply

On Tue, 2009-02-03 at 15:12 +0000, Joseph H Allen wrote: > I'm surprised that the Spartan-6 integrated memory controller does not support > ...

On Tue, 2009-02-03 at 15:12 +0000, Joseph H Allen wrote: > I'm surprised that the Spartan-6 integrated memory controller does not support > DIMMs. Also surprised that there are no integrated memory controllers in > Virtex-6. > I am not. From my experience with Virtex-5 and Spartan-3 I can say that Spartans are terribly slow. If you put MPMC into Virtex-5, you can reach pretty high dat


DDR2 SDRAM RELEATED PROBLEM IN SPARTAN 3A DSP 1800 + EDK 9.2i

Started by SUMAN in comp.arch.fpga13 years ago 4 replies

Hi, I am student using spartan 3a dsp 1800 board with EDK/ise 9.2i . In EDK I had used BSB to create new project using default...

Hi, I am student using spartan 3a dsp 1800 board with EDK/ise 9.2i . In EDK I had used BSB to create new project using default configuration for the following peripherals:- 1) microblaze (with bram 64KB) ,clock 2)RST32_UART 3)LED ,PUSH, DIP. 4)DDR2 SDRAM using MPMC peripheral I had used all default settings to the end of bsb. When i downloaded bitseam in the board , i got MEMORY TEST...


EDK/DDR Problem with HTG-V5-DDR3-PCIE Development Board

Started by luudee in comp.arch.fpga12 years ago

Howdy All, I have a HTG-V5-DDR3-PCIE-FX100 development board. It comes with custom XBD file, but I am having troubles using the DDR2...

Howdy All, I have a HTG-V5-DDR3-PCIE-FX100 development board. It comes with custom XBD file, but I am having troubles using the DDR2 memory. (It has both ddr2 and ddr3 memory). The I try to compile it I get: ERROR:MDT - issued from TCL procedure "check_partno" line 21 DDR2_SDRAM (mpmc) - The parameter C_MEM_PARTNO=EBE52UD6AJUA-6E-E is not found in the memory database. ER...


EDK/DDR Problem with HTG-V5-DDR3-PCIE Development Board

Started by Thyda Ly in comp.arch.fpga12 years ago

Howdy All, I have a HTG-V5-DDR3-PCIE-FX100 development board. It comes with custom XBD file, but I am having troubles using the DDR3...

Howdy All, I have a HTG-V5-DDR3-PCIE-FX100 development board. It comes with custom XBD file, but I am having troubles using the DDR3 memory. The I try to compile it I get: ERROR:MDT - issued from TCL procedure "check_partno" line 21 DDR2_SDRAM (mpmc) - The parameter C_MEM_PARTNO=EBE52UD6AJUA-6E-E is not found in the memory database. ERROR:MDT - platgen failed with error...


sharing sdram and parallel nor flash address/data bus using xilinx edk

Started by john1529 in comp.arch.fpga12 years ago 1 reply

The custom board that I am working on has a SDRAM and parallel NOR- FLASH, and they share the same address and data I/0 pins in the FPGA. SDRAM...

The custom board that I am working on has a SDRAM and parallel NOR- FLASH, and they share the same address and data I/0 pins in the FPGA. SDRAM uses mpmc controller and FLASH uses xps_mch_emc controller. Since they use different memory controllers I need to implement some logic in order to multiplex signals that come from the controllers to the external pins. Data buses are bidirectional whi...


mpmc kills plb bus on v4fx20

Started by bishopg in comp.arch.fpga12 years ago 3 replies

I am currently working on a design using the v4fx20. My current design consists of bram memory at 0xffff0000 to 0xffffffff and DDR...

I am currently working on a design using the v4fx20. My current design consists of bram memory at 0xffff0000 to 0xffffffff and DDR at 0x00000000 to 0x03ffffff. I can read and write from the bram memory, but whenever I either read or write from anywhere within the DDR memory space, my entire memory space (0x00000000 - 0xffffffff) becomes unusable. For example: XMD% mrd 0xffffff00 16 FFF...