How FPGA downconvert Giga SPS ADC data?

Started by fl in comp.arch.fpga10 years ago 6 replies

Hi, I have a question about ADC input to FPGA. Although I read some past thread on ADC connection with ADC. I still don't understand how...

Hi, I have a question about ADC input to FPGA. Although I read some past thread on ADC connection with ADC. I still don't understand how to downconvert Giga Hz adc in FPGA. The new ADC, for example ADC08D1500, can support 1.5GSPS or even more. Its manufacture gives the demo prototype which has Xilinx FPGA. To downconverter the ADC data, I think the FPGA digital filter must be upto 1.5GSPS. ...


Re: ADC implementation on fpga? Information and procudures wanted.

Started by pingboypulsar<spamoff>@hotmail.com in comp.arch.fpga12 years ago 1 reply

Yes i wish to interface to an external adc. Sorry if that was not clear. Hopefully the interfacing to an external adc is not too...

Yes i wish to interface to an external adc. Sorry if that was not clear. Hopefully the interfacing to an external adc is not too complicated. I wish to be able to connect industrial sensor(s) to an adc, and then acquire the value to the fpga for further processing. Maybe its better to use an asic or something else for interfacing an adc. I need to find out these things. Regards. ...


Interfacing ADS7230 ADC to Altera FPGA

Started by AlexKrish in comp.arch.fpga2 years ago 1 reply

Hi all, I want to implement an ADC Interface for an ADC - ADS 7230 (TI) in VHDL. I am not very familiar with ADCs to implement it in VHDL. I...

Hi all, I want to implement an ADC Interface for an ADC - ADS 7230 (TI) in VHDL. I am not very familiar with ADCs to implement it in VHDL. I already have an ADC Interface for a 10 bit ADC (MAX 1030) and a 12-bit ADC (LTC1407). Unfortunately these are in AHDL. Is it possible to use any of the existing ADC interfaces and adapt it to suit ADS 7230 in AHDL itself? If yes, what are the ne...


xilinx spartan 3 + 16 adc

Started by Anonymous in comp.arch.fpga10 years ago 8 replies

Hi I'd like to ask if that device will process data from 16 ADC (20 bit, 44,1kHz) to one output stream (does it depend on ADC clock - i...

Hi I'd like to ask if that device will process data from 16 ADC (20 bit, 44,1kHz) to one output stream (does it depend on ADC clock - i mean adc input clock = amount of output samples/s ? ) ? Or maybe i should consider using external input buffers ? thx in advance


OFFSET OUT with phase shift in DCM

Started by Sam Duncan in comp.arch.fpga14 years ago

Hi I have a design in which ADC data is clocked into a Virtex II using a clock provided by the ADC chip. The ADC data lags the rising edge of...

Hi I have a design in which ADC data is clocked into a Virtex II using a clock provided by the ADC chip. The ADC data lags the rising edge of the ADC clk by 13 ns. In order to compensate for this delay, I use a fixed phase shift in a DCM to generate the clock on which the data is registered and the internal logic runs. After registering and processing the ADC data, I send it off the Vir...


how to get the data from ADC

Started by senthil in comp.arch.fpga13 years ago 3 replies

hello friends, I am doing project in college. i want to know how to get the digital data from the ADC and store in the fpga Ram (say spartan...

hello friends, I am doing project in college. i want to know how to get the digital data from the ADC and store in the fpga Ram (say spartan II). pls give me some suggestions. actually, the design connected with the analog part. the analog part end will have ADC. how to get the data from the ADC.. regards senthil.R


Two-complement value from ADC, Spartan-3A, 3E

Started by m m in comp.arch.fpga9 years ago

Hi: I am testing a code for the Analog-to-Digital Converter that has the Spartan-3A FPGA Starter Kit (LTC1407A-1). The converted value from...

Hi: I am testing a code for the Analog-to-Digital Converter that has the Spartan-3A FPGA Starter Kit (LTC1407A-1). The converted value from the ADC is displayed on the LCD. Without sending voltage input to the VINA (Channel 0), when I command the ADC to take a sample of the channel, I get the 11111111111111 value as the digital value that the ADC converted. --> > Is it normal to get


Re: Why does two channels of ADC give different outputs?

Started by Jerry Avins in comp.arch.fpga12 years ago 16 replies
ADC

Frank wrote: > I am injecting the DAC output from TI DAC290x-EVM to ADC (Analog AD9218). > When I connect I channel from DAC to I & Q channel...

Frank wrote: > I am injecting the DAC output from TI DAC290x-EVM to ADC (Analog AD9218). > When I connect I channel from DAC to I & Q channel of ADC, I am seeing > vastly > different digital outputs on ADC (sampling three pins on oscilloscope). What > might > be the cause? Analog offset and gain difference is most likely. Nonlinearity is possible. Could a hold capacitor be defective?


How to constraint the In&Outputs of an ADC in XILINX ISE 9.2 (Virtex 4 LX 60)

Started by oliv...@googlemail.com in comp.arch.fpga9 years ago 5 replies

Hi everybody, in my design i have a timing problem with an ADC. I have this problem since my design has become more dense: This is the ADC...

Hi everybody, in my design i have a timing problem with an ADC. I have this problem since my design has become more dense: This is the ADC I'm using: AD677 (http://www.analog.com/static/ imported-files/data_sheets/AD677.pdf) My ADC-Entity has 3 inputs and 3 outputs. (see datasheet) BUSY: IN SCLK: IN SDATA: IN CAL: OUT CLK: OUT SAMPLE: OUT How do i now define the relationship ...


what is Timing generating before interfacing?

Started by Joshi & Joshi in comp.arch.fpga8 years ago 5 replies

Hi .. 'm having ADC chip "ADS 8364" wit 25m Hz input Clock . ADC output Signal Going to FPGA and its out signal going to processor fr...

Hi .. 'm having ADC chip "ADS 8364" wit 25m Hz input Clock . ADC output Signal Going to FPGA and its out signal going to processor fr further process. my problem is before writing vhdl Code i want generate timings ADC to FPGA but (1) i don no what is this timing generation ? (2) why this necessary before Code ? (3)Can any one give example timing code generation for ADC's Wait...


what is Timing generating before interfacing?

Started by Joshi in comp.arch.fpga8 years ago

Hi 'm having ADC chip "ADS 8364" wit 25m Hz input Clock . ADC output Signal Going to FPGA and its out signal going to processor fr further...

Hi 'm having ADC chip "ADS 8364" wit 25m Hz input Clock . ADC output Signal Going to FPGA and its out signal going to processor fr further process. my problem is before writing vhdl Code i want generate timings ADC to FPGA but (1) i don no what is this timing generation ? (2) why this necessary before Code ? (3)Can any one give example timing code generation for ADC's Waiting f...


FPGA interface to serial ADC

Started by Ki in comp.arch.fpga11 years ago 5 replies

I'm trying to get an FPGA (Spartan-II) to communicate with an ADC (Serial interface, with a maximum throughput rate of 2Msps and the maximum...

I'm trying to get an FPGA (Spartan-II) to communicate with an ADC (Serial interface, with a maximum throughput rate of 2Msps and the maximum signal bandwith I'm sampling is 200kHz). I've been using a counter to generate both the SCLK and CS signals and find that the ADC doesn't seem to be sampling. The SCLK signal on the ADC board looks distorted when I probe it with the scope and more worryi...


ADC implementation on fpga? Information and procudures wanted.

Started by pingboypulsar<spamoff>@hotmail.com in comp.arch.fpga12 years ago 3 replies

Hi This question has probably been asked a 1000 times. So here it is for 1001st time. How do I go about implementing an adc to a...

Hi This question has probably been asked a 1000 times. So here it is for 1001st time. How do I go about implementing an adc to a fpga? Hopefully someone can give me some areas to start in. Some links, reference materials, code etc. What are the most commonly interfaced adc's, and the buses they use? I currently am working with a spartan 3s 1500mb development board, and using the xili...


A strange behavior

Started by Marco in comp.arch.fpga12 years ago 2 replies

Hallo, I have made a small microcontroller based on microblaze. I have connected a differential 16 bit adc to my system. The adc takes input...

Hallo, I have made a small microcontroller based on microblaze. I have connected a differential 16 bit adc to my system. The adc takes input from a opamp for testing. The system works well only if I measure voltage between chipselect of adc and gnd. In this way it shows every hex number in range: 0 to 7FFF (it is two complementer). If not, I can see only 4-5 numbers of the acquisition...


Interface on board ADC to Spartan 3E startkit

Started by krunal in comp.arch.fpga10 years ago 1 reply

Hi, I want to interface on board ADC to spartan 3E startkit. Actually I am developing digital filter in FPGA for that I need ADC and...

Hi, I want to interface on board ADC to spartan 3E startkit. Actually I am developing digital filter in FPGA for that I need ADC and DAC interface with Spartan 3E. I have done with DAC but now I want to interface amplifier and ADC which are on board in Spartan 3E starter kit .........If any one have it's VHDL or Verilog code please give me..........Even I have find a document for imp...


DC Offset removal in FPGA

Started by Anonymous in comp.arch.fpga12 years ago 4 replies

Hi, we are reading an ADC o/p through FPGA. To remove the DC Offset present in the ADC input we have a DAC which can remove this DC offset...

Hi, we are reading an ADC o/p through FPGA. To remove the DC Offset present in the ADC input we have a DAC which can remove this DC offset using a subtractor before the actual analog input (with added DC offset) goes to ADC. Now I want my FPGA to calculate the DC offset from ADC outputs and then feed this value to DAC input which in turn cancel the DC offset using subtrator. can anyb...


ADC keeps outputting negative numbers, how?

Started by Frank in comp.arch.fpga12 years ago 3 replies
ADC

I have some digital waveforms, during the idle interval, it's zero, while in active mode, some patterns are output. This waveform is send...

I have some digital waveforms, during the idle interval, it's zero, while in active mode, some patterns are output. This waveform is send through DAC (TI DAC290x-EVM) and ADC (Analog AD9218). I am expecting a clean zeros during the idle interval, however the ADC output are not. How can I correct this problem? Thanks in advance.


Connecting ADC to Opb_Spi core

Started by Marco in comp.arch.fpga12 years ago 7 replies

Hallo, I'm trying to connect a Spi 16 bit ADC to Opb_Spi core. Where I could find some software examples? I have made some searches into...

Hallo, I'm trying to connect a Spi 16 bit ADC to Opb_Spi core. Where I could find some software examples? I have made some searches into Google but I don't have found anything. The only example into EDK documentation is about an eeprom. What is the meaning of : Status = XSpi_SetOptions(&Spi, XSP_MASTER_OPTION | XSP_MANUAL_SSELECT_OPTION); In this way ADC is a master? When acq...


OFFSET and Data Clock Skew?

Started by Brandon Jasionowski in comp.arch.fpga11 years ago 1 reply
ADC

Hello, I'm trying to register some data coming from an ADC at 4ns period. I currently have the following in my UCF: NET "adc_clk_p"...

Hello, I'm trying to register some data coming from an ADC at 4ns period. I currently have the following in my UCF: NET "adc_clk_p" TNM_NET = "TG_adc_clk_p"; TIMESPEC "TS_adc_clk_p" = PERIOD "TG_adc_clk_p" 4 ns HIGH 50%; NET "adc?_db_p " OFFSET = IN 1.0 ns BEFORE "adc_clk_p"; NET "adc?_db_n " OFFSET = IN 1.0 ns BEFORE "adc_clk_n"; However, the adc data arrives 2.5


FPGA board with an ADC

Started by maverick in comp.arch.fpga10 years ago

Hi, I am looking for an FPGA board with preferably a Xilinx FPGA (Spartan 3 or Virtex series) with 500k to 1 million gates capacity. The...

Hi, I am looking for an FPGA board with preferably a Xilinx FPGA (Spartan 3 or Virtex series) with 500k to 1 million gates capacity. The board should have any or all of the following interfaces. USB 2.0 (preferred) Serial Port Ethernet The board must have a single or dual channel ADC with sampling speed in the range of 10-20 MS/s. ADC resolution should be somwhere around 12-16 bits. ...