cpu,fpga, clock, dac, initialize sequence

Started by Anonymous in comp.arch.fpga11 years ago 2 replies
ADC

i'm dealing a board which has cpu,fpga, clock, adc etc. onboard. the clock is for board timing for both the fpga and adc. the init sequence...

i'm dealing a board which has cpu,fpga, clock, adc etc. onboard. the clock is for board timing for both the fpga and adc. the init sequence was to load the fpga logic first, then the clock, then the adc. but fpga guys say it's wrong. should i init clock and adc first, then the fpga? what's the point here?


High-speed ADC+ Rocket I/O capability FPGA board

Started by Vivek Menon in comp.arch.fpga13 years ago 4 replies

Hi everyone, I am looking to buy a board that has the following features: 1. High-speed ADC 2. Xilinx Virtex-2Pro or Virtex-4 FPGA with Rocket...

Hi everyone, I am looking to buy a board that has the following features: 1. High-speed ADC 2. Xilinx Virtex-2Pro or Virtex-4 FPGA with Rocket I/O capability I looked at the Xilinx development boards (the matrix_Xdev_board brochure) and could not find one with Rocket I/O and the ADC. The closest product I have with a high-speed ADC and an FPGA is National Semiconductor's ADC08D1500 Dev bo...


DCM Jitter?

Started by Clark Pope in comp.arch.fpga16 years ago 7 replies

I had planned to generate an ADC clock from a DCM block in my VirtexII. I'm told the jitter on the DCM output clock is likely to degrade the...

I had planned to generate an ADC clock from a DCM block in my VirtexII. I'm told the jitter on the DCM output clock is likely to degrade the ADC performance. The ADC clock is 56 MHz. The source clock will be 8MHz so I need 7x in the DCM. Is the jitter really a major problem at 56MHz? Thanks, Clark


CycIII Intefacing these new serial ADC's

Started by LC in comp.arch.fpga11 years ago

Hi, I'm on a design that requires 2 fast ADC (14bit 100Ms/s) and an FPGA. So far all all plans were based on parallel data to the FPGA,...

Hi, I'm on a design that requires 2 fast ADC (14bit 100Ms/s) and an FPGA. So far all all plans were based on parallel data to the FPGA, but I must confess these new serial ADC's are tempting specially the ADS6244 that fits perfectly with my intentions. (2ch 14bit 125Ms/s in a single package and a few lvds lines only interfacing the FPGA) But I fear the interfacing to an ALtera Cyclo...


DCM input clock

Started by Andyman in comp.arch.fpga16 years ago 1 reply

Hi all, I have a design which takes data from an external ADC. The ADC provides a 35 Mhz clock. Currently the design feeds the input clock...

Hi all, I have a design which takes data from an external ADC. The ADC provides a 35 Mhz clock. Currently the design feeds the input clock through a DCM and uses the 180 degree phase shifted version to sample and reassemble the ADC data. This all then passes to our system clock domain via one of the (wonderfully useful) Xilinx self addressing asychronous FIFO's. As this is for a com...


FPGA board to interface with ADC (>10 GHz) and generate 5Gbps PRBS

Started by vmenon in comp.arch.fpga4 years ago
ADC

Hello all, I am designing a circuit that requires a 10 GHz ADC and a FPGA to generate a 5 Gbps PRBS. I am not able to find a high speed ADC and...

Hello all, I am designing a circuit that requires a 10 GHz ADC and a FPGA to generate a 5 Gbps PRBS. I am not able to find a high speed ADC and a supporting FPGA evaluation board. Does anyone know/ can recommend a board? Thanks in advance, V


ADC Clock on Stratix II DSP Dev Board

Started by Paul Solomon in comp.arch.fpga14 years ago 1 reply

Hello, I recentally purchased a Stratix II (60) DSP Dev Board (from Altera) and I have been having a bit of trouble getting the ADC to work...

Hello, I recentally purchased a Stratix II (60) DSP Dev Board (from Altera) and I have been having a bit of trouble getting the ADC to work correctly and I was wondering is there was anyone therer that had experience with this board. I am able to get it to work when the clk is set to 100MHZ, but is I use a PLL to run the clk at say 80MHz then the data that I read from the ADC (also ...


FPGA DAC Interface

Started by Sharath Raju in comp.arch.fpga9 years ago 4 replies

Hello everyone, We are building a board in which we propose to design the FPGA interface to a DAC in the following manner. Please give...

Hello everyone, We are building a board in which we propose to design the FPGA interface to a DAC in the following manner. Please give feedback whether such an approach is feasible. Functionality: Among other things, the board contains three components: ADC, DAC and FPGA (XC3SD1800A, Spartan 3ADSP 1.8 million gates). The ADC & DAC are connected to the FPGA. The ADC, DAC and FPGA are all...


OFFSET Constraining a Signal behind a DCM?

Started by Christian Wiesner in comp.arch.fpga13 years ago

Hi, I have a design, where I want to interface an ADC (250 MHz) to a Spartan-3E. The clock from the ADC enters the FPGA via LVDS, gets...

Hi, I have a design, where I want to interface an ADC (250 MHz) to a Spartan-3E. The clock from the ADC enters the FPGA via LVDS, gets IBUFGDSed and enters the DCM. It leaves the DCM as CLOCK_0 and half the inputclock, CLOCK_DV. CLOCK_0 then clocks a IP-Core FIFO. Meanwhile, the DATA from the ADC (LVDS as well) enter the FPGA and are routed into the 8-bit input of the FIFO. There I wa...


Virtex 5 Rocket IO design for reading in ADC data.

Started by jgk2004 in comp.arch.fpga8 years ago 11 replies

Hello all, I am presently working with a virtix 5 FPGA and trying to get the rocket IOs to work with reading in the data generated from my ADC....

Hello all, I am presently working with a virtix 5 FPGA and trying to get the rocket IOs to work with reading in the data generated from my ADC. The ADC is clocked at 500MHz and I have 5 LVDS outputs, my clock at 500MHz and my data 4 bits transitioning at 250Mhz. I am then configuring the FPGA to store the data after it has been serial to parallel converted within the FPGA then I read it out lat...


ADC capture with FPGA Spartan3 in Verilg

Started by Jhoberg in comp.arch.fpga12 years ago
ADC

Hello, This source is a capture the ADC0804 with FPGA Spartan3, Oscillator 50MHz frequency Clk for ADC is 650KHz, sampling frequency 8Hz, show...

Hello, This source is a capture the ADC0804 with FPGA Spartan3, Oscillator 50MHz frequency Clk for ADC is 650KHz, sampling frequency 8Hz, show the data capture in array leds. //##############adc08.v################### //#########Develp by Jhoberg Quevedo############ //#########email: jrquevedor@gmail.com########### module adc08(clkadc,adc,adccs,adcwr,adcintr,led,osc); parameter Nosc=3...


working with ADC and DAC together

Started by mlajevar in comp.arch.fpga10 years ago 1 reply

Hello I have the vhdl code for both amplifier-ADC and DAC of spartan3E,now I want to combine them together.Actually the purpose is to get an...

Hello I have the vhdl code for both amplifier-ADC and DAC of spartan3E,now I want to combine them together.Actually the purpose is to get an analog avlue from oscilloscope send it to FPGA(through my vhdl code for ADC ,it is converted to digital,and via the code for DAC, it will be converted to analog voltage)and check the analog output to see if it is similar ti the analog input we applied to A...


Propagation delay sensitivity to temperature, voltage, and manufacturing

Started by folnar in comp.arch.fpga13 years ago 2 replies

We currently have a Spartan 3 FPGA in our design. In our design, we are using two DCM's specifically. One is driving an off-chip ADC and...

We currently have a Spartan 3 FPGA in our design. In our design, we are using two DCM's specifically. One is driving an off-chip ADC and the other is driving an FPGA register (which registers the data coming back from the off-chip ADC). One clock is manually phase-shifted at synthesis relative to the other clock to resolve clock skew issues between the ADC processing of the data and the outp...


virtex-5 lvds termination issue?

Started by Muzaffer Kal in comp.arch.fpga10 years ago 6 replies

Hi, I've been working on a high speed ADC board which has a LVDS outputs connected to a virtex-5 lx 50. The ADC board has 100 ohm...

Hi, I've been working on a high speed ADC board which has a LVDS outputs connected to a virtex-5 lx 50. The ADC board has 100 ohm differential lines but no receiver termination so I configured the IOs on the FPGA side to be LVDS_25 with DIFF_TERM option on. I connected the ADC board to the FPGA board and did a capture with a chipscope block and the data was what we'd expect. The problem star...


How can I surpress noise in an ADC board?

Started by Frank in comp.arch.fpga14 years ago 7 replies
ADC

While I have only a 40MHz clock connected to a 10 bit ADC, nothing connected to the analog input sockets, the chip is Analog AD9218 (ADC chip)...

While I have only a 40MHz clock connected to a 10 bit ADC, nothing connected to the analog input sockets, the chip is Analog AD9218 (ADC chip) EVM board. On the LA, sampled outputs are 0~16 for one channel, -32~0 for the other channel (400 MHz timing mode). Is my board faulty? According to my simulation in digital design, my sampled inputs (10 bits each) can not have noise higher than 1 ...


Stratix EP1S80 DSP development board (Problem for ADC/DAC conversion )

Started by ylc199 in comp.arch.fpga14 years ago 2 replies

Hi I have a Stratix EP1S80 DSP development board. However, i am not able to get the ADC or the DAC devices on the board to work. What i am...

Hi I have a Stratix EP1S80 DSP development board. However, i am not able to get the ADC or the DAC devices on the board to work. What i am trying to do is simply send an analog waveform (eg 1 khz sine wave) into the adc and then try to recover the waveform with the DAC. Can anyone please kindly advice on this or even better if anyone have a design example that can email me? Thanks regard...


built in adc in fpga????

Started by shrinivas gotur in comp.arch.fpga6 years ago 6 replies
ADC

hi guys, i was wondering whether can i have built in adc in fpga with good (say 12 or 14 bit) resolution and 0-5v input range will be...

hi guys, i was wondering whether can i have built in adc in fpga with good (say 12 or 14 bit) resolution and 0-5v input range will be available in market. please revert back soon if u know any.i am waiting


Need flash adc with plcc format?

Started by Anonymous in comp.arch.fpga13 years ago 6 replies
ADC

Is there a flash adc with a plcc package, anything above 24MHz minimum sample rate will suit me. tnx

Is there a flash adc with a plcc package, anything above 24MHz minimum sample rate will suit me. tnx


Current from FPGA pins to ADC

Started by Anonymous in comp.arch.fpga13 years ago 6 replies

I want to use a Spartan II chip to drive two ADCs. The ADC spec says that the input current on the SCLK pin is +/-0.5uA max and 10nA typically....

I want to use a Spartan II chip to drive two ADCs. The ADC spec says that the input current on the SCLK pin is +/-0.5uA max and 10nA typically. Similary the input current on the CS pin is 10nA typically. The absolute maximum ratings for the same ADC state that the maximum input current to any pins (except supplies) is +/-10mA. I'm using the LVTTL standard and can only specify the drive curren...


FPGA/DSP system design problem

Started by Anonymous in comp.arch.fpga10 years ago 3 replies

Dear All: I am thinking about my system, the picture is here: http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/ I want to...

Dear All: I am thinking about my system, the picture is here: http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/ I want to transfer the raw/processed image sensor data to USB 2.0 or dpram. Two choices: 1. ADC -> DSP, this means parallel ADC, then DSP processed data -> USB, FPGA works as a coprocessor, use FPGA's DSP (difficult), FPGA- > DPRAM 2. ADC -> FPGA, this m