how to choose the FPGA/DSP coprocessor system architecture

Started by Anonymous in comp.arch.fpga10 years ago 1 reply

Dear All: I am thinking about my system, the picture is here: http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/ I want to...

Dear All: I am thinking about my system, the picture is here: http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/ I want to transfer the raw/processed image sensor data to USB 2.0 or dpram. Two choices: 1. ADC -> DSP, this means parallel ADC, then DSP processed data -> USB, FPGA works as a coprocessor, use FPGA's DSP (difficult), FPGA- > DPRAM 2. ADC -> FPGA, this mea


LVDS

Started by maxascent in comp.arch.fpga14 years ago 3 replies

I am routing a pcb with a fpga and adc which has LVDS outputs. I am trying to match the length of the signals. Will I be ok to match them to...

I am routing a pcb with a fpga and adc which has LVDS outputs. I am trying to match the length of the signals. Will I be ok to match them to within 1mm. The max length of any signal will be 33mm and the adc is clocked at 250MHz. Thanks Jon


Reading from ADC and writing to DAC at same time

Started by Nicholas Kinar in comp.arch.fpga10 years ago 30 replies

Hello-- I'm setting up a circuit where I need to write data to a DAC at the same time as read data from 8 ADCs. I need to shift a data...

Hello-- I'm setting up a circuit where I need to write data to a DAC at the same time as read data from 8 ADCs. I need to shift a data word out to the DAC to set an output voltage. At the same time, I need to read data from each ADC. The DAC and the ADCs all communicate over SPI. The maximum sampling rate of each 18-bit ADC is 400 kHz. The maximum update rate of each 16-bit DAC...


Interfacing an 1GS ADC

Started by Alex in comp.arch.fpga15 years ago 9 replies

Hi, It's not the first time this question has been asked, but I'd like to know todays state of art: Are their any devices at Altera, Xilinx...

Hi, It's not the first time this question has been asked, but I'd like to know todays state of art: Are their any devices at Altera, Xilinx or others, capabable of handling the fast throughput of high-speed ADCs (1 GS), such as Atmel's AT84AD001B or NS ADC08D1000 ? Preferably without an external DMUX-device... Using the ADC's internal DEMUX leaves us with 16 500 MHz LVDS lines per channe...


[FS]: ADS5500IPAP ADC 14BIT 125MSPS 64-HTQFP

Started by Anonymous in comp.arch.fpga14 years ago
ADC

Dear colleage engineers, I have for sale twenty-eight ADS5500IPAP (ADC 14BIT 125MSPS 64-HTQFP), of course unused, sealed and in perfect...

Dear colleage engineers, I have for sale twenty-eight ADS5500IPAP (ADC 14BIT 125MSPS 64-HTQFP), of course unused, sealed and in perfect conditions. If seriously interested please mail me, my address is: microelectro gmail com Best regards, Mario


High-speed DAC/ADC with FPGA

Started by rnbrady in comp.arch.fpga13 years ago 16 replies

Hi folks I'm working with an Altera Stratix ep1s10 on a development board. The data sheet says the IO can operate at rates up to 800 MSPS. If...

Hi folks I'm working with an Altera Stratix ep1s10 on a development board. The data sheet says the IO can operate at rates up to 800 MSPS. If I have a look on the internet, I see DAC and ADC technology going up to 400 MSPS. My application is software defined radio, where the general mantra is to do as little analog front-end as possible, i.e. sample as fast as you can. What are the l...


ADC problem on spartan3E

Started by mlajevar in comp.arch.fpga10 years ago 8 replies

Hello I wrote a vhdl code for implementing amplifer and ADC on sparan3E board, I am working with LTC1407A-1 Dual A/D on spartan3E(with SPI...

Hello I wrote a vhdl code for implementing amplifer and ADC on sparan3E board, I am working with LTC1407A-1 Dual A/D on spartan3E(with SPI protocol),my problem is when I changed the analog voltage which is applied to this A/D,the eight most significant digital value on LEDs also changed accordingly,but it's not equal to what I calculated based on the formula D[13:0]=(Gain*(Vin-1.65)*8192)/1.25...


Trigger implementation on ADC-FPGA

Started by Syed Huq in comp.arch.fpga5 years ago 8 replies

Hi, I'm trying to implement hardware trigger functionality by modifying the FPG= A code for the LM97600RB from Texas Instruments which uses a...

Hi, I'm trying to implement hardware trigger functionality by modifying the FPG= A code for the LM97600RB from Texas Instruments which uses a Virtex-5 FPGA,= and then implementing it on our custom board but I had a few questions wit= h regards to it.=20 From what I understand of how the trigger works, the data keeps being captu= red continuously by the ADC, but the trigger functionality...


clock skew as an asset

Started by rosaldorosa in comp.arch.fpga10 years ago 1 reply
ADC

I'm working on the high frequency project where I have adc converter able to scan Analog signal much faster then fpga. Is is possible to send a...

I'm working on the high frequency project where I have adc converter able to scan Analog signal much faster then fpga. Is is possible to send a reference clock to ADC, then divide it (by 4 for example), and the resulting clock move in phase ( intentionally skew) into 4 phase shifted clocks. The simple parallel logic to multiply subtract. Is it possible at all? Does anyone has seen su...


ADC card selection for C6713

Started by murselonder in comp.arch.fpga13 years ago
ADC

Hi all I want to receive 70 MHz PM+BPSK modulated signal. Video bandwidth:138 kHz Modulation index for PM: 1.2 radian Subcarrier frequency...

Hi all I want to receive 70 MHz PM+BPSK modulated signal. Video bandwidth:138 kHz Modulation index for PM: 1.2 radian Subcarrier frequency of BPSK:65536 Hz. I have been using Matlab /Simulink and TMS320C6713 DSK. 1. I need suitable ADC daughtercard for C6713 DSK. 2. What is the sampling rate according to this spec.s? How can I calculate? I want to proof my calculation method. ...


Delta-Sigma in an FPGA

Started by Rob Gaddi in comp.arch.fpga8 years ago 8 replies
ADC

Hey all -- So I've got yet another project making me say "Gosh it'd be nice to be able to implement a DAC/ADC directly in the FPGA." And so...

Hey all -- So I've got yet another project making me say "Gosh it'd be nice to be able to implement a DAC/ADC directly in the FPGA." And so I looked around and found all the same white papers I always find wherein a first-order delta-sigma modulated ADC or DAC is implemented using only an FPGA and an RC filter. I've done the DAC one before, but only in closed loop situations where ...


what is the correct way to capture ADC using fpga

Started by cutemonster in comp.arch.fpga12 years ago 8 replies

Hi, can anyone tell me what is the correct way to capture data from 60 mhz sampling, 16 bits ADC? Should I use 4 different phase...

Hi, can anyone tell me what is the correct way to capture data from 60 mhz sampling, 16 bits ADC? Should I use 4 different phase shifted clock,0,90,180,270 with DCM and then decided which one work the best? If my system clock is different than sampling clock, how can I synchronize the data? should I should BRAM? thank you so much,


Re: clock skew as an asset

Started by Anonymous in comp.arch.fpga10 years ago

Yes, reference the DCM instructions. ---Matthew Hicks > rosaldorosa pisze: > > > I'm working on the high frequency project where I...

Yes, reference the DCM instructions. ---Matthew Hicks > rosaldorosa pisze: > > > I'm working on the high frequency project where I have adc converter > > able to scan Analog signal much faster then fpga. > > Is is possible to send a reference clock to ADC, then divide it (by 4 > > for example), and the resulting clock move in phase ( intentionally > > skew) into 4 phase shifted clocks.


FSL or DMA w/ FIFO?

Started by Anonymous in comp.arch.fpga11 years ago 7 replies

Hello everyone, My project has several ADC channels with 16bit data up to 24kSPS. There is no need for each ADC sample to be sent ASAP to...

Hello everyone, My project has several ADC channels with 16bit data up to 24kSPS. There is no need for each ADC sample to be sent ASAP to the microblaze, as the data is processed in chunks of 200 samples. A previous (non-xilinx) version of this project used a FIFO and a burst read over a PCI bus to a pentium processor. Now, reading about FSL it seems that the microblaze has to execute...


delta sigma adc.....

Started by krunal in comp.arch.fpga11 years ago 21 replies

hi....I want to implement Sigma Delta ADC in Spartan 3E starter kit....i have implemented it as xilinx's xapp-155.....in ise it works well for 8...

hi....I want to implement Sigma Delta ADC in Spartan 3E starter kit....i have implemented it as xilinx's xapp-155.....in ise it works well for 8 bit....but give problem for 16 bit.....When i open it in sysgen it now work.......actually in program the dac.v is included......i dont know how to open that include file in sysgen....please help........if any one have verilog or vhdl code for that ...


PCIe latency

Started by Anonymous in comp.arch.fpga13 years ago 2 replies

Hi Im trying to design a high speed data capture card. Im using a Lattice ECP2M-50 FPGA with the one-board SERDES units (MGBT in...

Hi Im trying to design a high speed data capture card. Im using a Lattice ECP2M-50 FPGA with the one-board SERDES units (MGBT in Xilinx dtasheets). Im using a MSPS Nation ADC. This dual ADC has a output of 1Gb/s and thus the combined x4 lane PCIe will match this rate. HOWEVER, if there is latency on the PCIe bus more than 100us then my RAM inside the FPGA will overflow. I need to know bus ...


How to connect two BNC connectors to FPGA board?

Started by Alex in comp.arch.fpga10 years ago 5 replies

Hello All, In my project some RF input from outside circuitry has to be converted into digital form in ADC and then, after processing in FPGA,...

Hello All, In my project some RF input from outside circuitry has to be converted into digital form in ADC and then, after processing in FPGA, it will be converted back into analog RF signal which is to be displayed on an oscilloscope. Hence, I am interested - how to connect BNC connectors to ADC and DAC present on Xilinx Spartan-3E 1600E Microblaze Development Board? Thank you.


Did National cheat with the Virtex 4

Started by lecr...@chek.com in comp.arch.fpga13 years ago 13 replies

I was watching Avnets' sponcered video with Robert Pease and Howard Johnson where National had a board with a ADC08D1500 dual ADC tied directly...

I was watching Avnets' sponcered video with Robert Pease and Howard Johnson where National had a board with a ADC08D1500 dual ADC tied directly into a Virtex 4. The videos, datasheets, etc may be found at: http://www.national.com/xilinx/ The LVDS clock coming from the ADC is 750MHz. They route this clock directly to the Virtex 4. When I look at the specs. for the Virtex 4, this would ...


Source Synchronous LVDS Design - Phase Shift in the Timing Analysis?

Started by Christian Wiesner in comp.arch.fpga13 years ago 2 replies

Hi, I plan to interface a 250MHz ADC with an Spartan 3E-1600. The ADC gives out 8 data lines and 1 clock line, all via LVDS. The data should...

Hi, I plan to interface a 250MHz ADC with an Spartan 3E-1600. The ADC gives out 8 data lines and 1 clock line, all via LVDS. The data should be captured an put into a blockram. The OFFSET IN constraint, which I want to meet, says, that the DATA should be available 0.97ns before the CLOCK. So far I have the data-lines into their IBUFDS (8 times) and into the data-input of the BRAM. Clock...


save data from adc in text file

Started by nola94 in comp.arch.fpga10 years ago 5 replies

hi all, i am using spartan 3e starter kit and i want to save the data captured from onboard adc(14 bit word) to a text file...at the moment i use...

hi all, i am using spartan 3e starter kit and i want to save the data captured from onboard adc(14 bit word) to a text file...at the moment i use edk and write my results on the screen through rs232 using microblaze...how i can save the data in a text file? i tried by using fprintf but i get the following errors: TestApp_Memory_microblaze_0/src/TestApp_Memory.c:53: warning: assignment makes p...