Dealing with SPI ADC timings

Started by ElVale in comp.arch.fpga10 years ago 3 replies
ADC

I'd like to implement an SPI master to read an AD7924 ADC. The thing is that there are some setup and hold time I have to respect, ie CS'to...

I'd like to implement an SPI master to read an AD7924 ADC. The thing is that there are some setup and hold time I have to respect, ie CS'to SCLK setup time, SCLK to DOUT valid hold time, etc. They go from typically 10 ns to 50 ns. What's the best way to implement these delays?


FPGA Board and a adc working between 20MHz and 100MHz

Started by in comp.arch.fpga9 years ago 2 replies
ADC

Hi, I need an information. I need to have an FPGA Board and recive from a adc working between 20MHz and 100MHz, but i don't have any idea...

Hi, I need an information. I need to have an FPGA Board and recive from a adc working between 20MHz and 100MHz, but i don't have any idea who to do it because i don't know any site that sells this things together! Thanks for the attention


Slave PLB core interrupt

Started by Manny in comp.arch.fpga12 years ago 2 replies

Hello, Just finished writing an ADC driver which I connected to a PPC via PLB (slave configuration). I have also instantiated a OPB...

Hello, Just finished writing an ADC driver which I connected to a PPC via PLB (slave configuration). I have also instantiated a OPB interrupt controller to which I'm trying to register my ADC driver interrupt. However, so far I couldn't manage to register my interrupt handler--- SDK keeps on giving me this weird error message whenever I attempt to register my external interrupt through XEx...


Audio interface in Spartan 3E Starter kit

Started by FPGA in comp.arch.fpga13 years ago 1 reply

Hi All, I like to use the Spartan 3E Starter kit as audio capture/playback developping system as it has Linear Technology's DAC and ADC built...

Hi All, I like to use the Spartan 3E Starter kit as audio capture/playback developping system as it has Linear Technology's DAC and ADC built in. Ideally I want to be able to connect it to a computer speaker and microphone just like a computer sound card. But I guess it requires some external analog circuit and also the line-in and line-out connector to interfac with the DAC and ADC. Is...


ADC (LTC1407a) on Xilinx Spartan 3E starter kit

Started by Ju, Jian in comp.arch.fpga13 years ago 1 reply

Hi all, I'm trying to run the ADC chip LTC1407a on the spartan 3e starter kit. Both the function and timing simulation is validated and the...

Hi all, I'm trying to run the ADC chip LTC1407a on the spartan 3e starter kit. Both the function and timing simulation is validated and the signal AD_CONV and SPI_SCK is just as wanted when I use an oscilloscope to observed the board signal. In other words, 34 SPI_SCK after 1 clock period of AD_CONV. However, the data output is always 0x3FFF when a 10kHz sine wave is applied on both c...


ADC by using counter method on FPGA using VHDL language

Started by VIJAY KUMAR in comp.arch.fpga8 years ago 2 replies

Hello,i have some idea about vhdl.I want coding of ADC by using counter method on FPGA by using VHDL.. I know the some idea about this program...

Hello,i have some idea about vhdl.I want coding of ADC by using counter method on FPGA by using VHDL.. I know the some idea about this program the following process. a) first reset the counter b)the references and analog voltages are equal then gate can be closed.then the the value can be stored in the couters i.e., the value in counter is equavalent to digital value to analog input. I wa...


Strange behavior with serial ADC chip select and MISO pin

Started by Nicholas Kinar in comp.arch.fpga10 years ago 4 replies

Hello-- I am working on a custom board with a Cyclone II FPGA. Attached to the pins of the FPGA are six serial ADCs (AD7690 from Analog...

Hello-- I am working on a custom board with a Cyclone II FPGA. Attached to the pins of the FPGA are six serial ADCs (AD7690 from Analog Devices). Each ADC has three pins which are controlled by the FPGA: #CS, MISO, SCLK and CNV. I am using the ADCs with the #CS-mode, 3-wire with busy signal interface. This means that a rising edge on CNV will initiate a conversion, and since #CS...


Implementation Issue

Started by James in comp.arch.fpga8 years ago 3 replies

Hi Guys, I'm using the Spartan-3E 1600E Microblaze development kit. What I'm basically doing is writing to the on board DAC (Linear...

Hi Guys, I'm using the Spartan-3E 1600E Microblaze development kit. What I'm basically doing is writing to the on board DAC (Linear Tech LTC2624 Quad DAC), and then reading from the on board ADC (Linear Tech LTC6912 Dual A/D) whose analog input is connected to the DAC analog output. The data written to the DAC and the data read from the ADC is then made available to other modules within my des...


8-bit word to 4-digit, 7-segment display

Started by weizbox in comp.arch.fpga15 years ago 2 replies
ADC

Hello, Im pretty new to FPGAs in general and so far have gotten some basic things down such as get data from my ADC and be able to...

Hello, Im pretty new to FPGAs in general and so far have gotten some basic things down such as get data from my ADC and be able to hardwire certin values into my 4 digit 7-segment display, but now I need to combine the two and Im not sure how. Basicly I get an 8-bit binary number from my ADC, from there how would I turn that number into usable values to display on my 4-digit 7-segment disp...


FPGA DSP basics: clock enable / new clock

Started by o pere o in comp.arch.fpga7 years ago 7 replies

My current goal is to implement some digital signal processing (filters) on a FPGA. I am currently using Terasics DE0 nano board. This board has...

My current goal is to implement some digital signal processing (filters) on a FPGA. I am currently using Terasics DE0 nano board. This board has an ADC128S022 ADC. I have started as follows: From the 50 MHz board reference I derive a 25.6 MHz signal with a PLL. From this clock I generate the signals required to drive the ADC, essentially a clock at 3.2 MHz. Every 16 clock cycles, the ...


doubts regarding fpga spartan3E kit use.

Started by cpfpga in comp.arch.fpga10 years ago

I am newbie in using FPGA and while using spartan3E starter kit I have two doubts. 1.I am making a simple ADC to DAC system using on board ADC...

I am newbie in using FPGA and while using spartan3E starter kit I have two doubts. 1.I am making a simple ADC to DAC system using on board ADC and DAC chips.Do I have to provide 3.3 volt( for creating reference voltage) to header J5 through external power supply, or does the board has its our circuitry to provide that internally(from its own power)?I think same will go for GND too. 2.I have to s...


Image Sensor Interface.

Started by ertw in comp.arch.fpga11 years ago 16 replies
ADC

Hi, I am planning to read an image sensor using an FPGA but I am a little confused about a bunch of things. Hopefully someone here can help me...

Hi, I am planning to read an image sensor using an FPGA but I am a little confused about a bunch of things. Hopefully someone here can help me understand the following things: Note: The image sensor output is an ANALOG signal. Datasheet says that the READOUT clock is 40MHz. 1. How is reading of an image sensor using an ADC different then reading a random analog signal using an ADC? ...


Spartan3E Starter Kit MISO and Flash pin shared

Started by mstanisz in comp.arch.fpga10 years ago 11 replies

Hi, I've been working on a Spartan3E Starter Kit and I've hit a snag while using both the onboard ADC and the StrataFlash PROM. The SPI bus...

Hi, I've been working on a Spartan3E Starter Kit and I've hit a snag while using both the onboard ADC and the StrataFlash PROM. The SPI bus MISO signal for the ADC and the memory's bit0 for its data are the same net. Could anyone explain how to map the MISO and data pin to the same NET? I've tried doing it in the MHS and UCF files in the Xilinx EDK, but it doesn't seem to hold. I think I ma...


ISE or EDK?

Started by Vagant in comp.arch.fpga12 years ago 3 replies

Hello, I want to design a system which includes ADC, digital filter, DAC with dataflow chart like this: audio_signal1-> ADC-> digital...

Hello, I want to design a system which includes ADC, digital filter, DAC with dataflow chart like this: audio_signal1-> ADC-> digital filter-> DAC-> audio_signal2 digital filter has to be controlled from PC host running Windows through a GUI written in Visual Basic. Which software from Xilinx is more appropriate to design such system - WebPack ISE or EDK?


confusion with ADC/DAC interface implementation

Started by Anonymous in comp.arch.fpga9 years ago 6 replies
ADC

Hi, i am confused regarding the ADC/DAC interface implementation on FPGA. I have read a code where after serialising the input data of 16...

Hi, i am confused regarding the ADC/DAC interface implementation on FPGA. I have read a code where after serialising the input data of 16 bits in 16 clock cycles, the interface logic loops (in vain?) for another 16 cyles before serialising the next data. can#t understand why? why the serialisation of the next data is not done immediately. moreover, should the serialisation clock rate be 16 ...


FPGA board with 4 channel 500Msps ADC?

Started by wzab in comp.arch.fpga6 years ago 5 replies

Hi, I'm looking for possibly cheap FPGA based board with 4 channel 500 Msps ADC (at least 8bit). The board should allow preprocessing of...

Hi, I'm looking for possibly cheap FPGA based board with 4 channel 500 Msps ADC (at least 8bit). The board should allow preprocessing of acquired data and transmission of results to the PC (via PCIe, Ethernet or USB - the amount of data after preprocessing will be significantly reduced). I have found boards like: http://www.signatec.com/products/daq/high-speed-digitizer-fpga-pcie-board...


Dynamic DCM Controller help

Started by cutemonster in comp.arch.fpga13 years ago

Hi, I'm interfacing 2 ADC to spartan 3 3s400. I need to phase shift the "DATA READY" from ADC with DCM and I'm not succeed. First of all, is it...

Hi, I'm interfacing 2 ADC to spartan 3 3s400. I need to phase shift the "DATA READY" from ADC with DCM and I'm not succeed. First of all, is it a good idea to phase shift the DATA READY signal for data capturing purpose? I did 90,180 and 270 shift and I did see some change. Now I would like to use dynamic shift and here is my code. The problem is that status[0] always high and the phase shift D...


Dynamic DCM Controller help

Started by cutemonster in comp.arch.fpga13 years ago

Hi, I'm interfacing 2 ADC to spartan 3 3s400. I need to phase shift the "DATA READY" from ADC with DCM and I'm not succeed. First of all, is it...

Hi, I'm interfacing 2 ADC to spartan 3 3s400. I need to phase shift the "DATA READY" from ADC with DCM and I'm not succeed. First of all, is it a good idea to phase shift the DATA READY signal for data capturing purpose? I did 90,180 and 270 shift and I did see some change. Now I would like to use dynamic shift and here is my code. The problem is that status[0] always high and the phase shift D...


Dynamic DCM Controller help

Started by cutemonster in comp.arch.fpga13 years ago

Hi, I'm interfacing 2 ADC to spartan 3 3s400. I need to phase shift the "DATA READY" from ADC with DCM and I'm not succeed. First of all, is it...

Hi, I'm interfacing 2 ADC to spartan 3 3s400. I need to phase shift the "DATA READY" from ADC with DCM and I'm not succeed. First of all, is it a good idea to phase shift the DATA READY signal for data capturing purpose? I did 90,180 and 270 shift and I did see some change. Now I would like to use dynamic shift and here is my code. The problem is that status[0] always high and the phase shift D...


Serial LVDS ADC to spartan6

Started by Thomas Heller in comp.arch.fpga7 years ago 2 replies

I have to connect a dual 12-bit ADC with serial LVDS outputs (2-lanes per converter) to a spartan 6 FPGA. It would be ideal if I can use a...

I have to connect a dual 12-bit ADC with serial LVDS outputs (2-lanes per converter) to a spartan 6 FPGA. It would be ideal if I can use a single HDMI connector for this. The converters I'd like to use are the ADS6224 or ADC12S105, running at 100 MHz sample rate. They have 6 data LVDS data outputs: 4 data lines, 1 frame clock and 1 bit clock. Since the HDMI connection only has 5 differ...