Connecting ADC chip to sparta 3 a dsp

Started by lakshmi3489 in comp.arch.fpga10 years ago 2 replies

hi there I have an ADC chip which is working in the LVDS mode. The data out(D0+,D0-,......D13+ and D13-),along with data...

hi there I have an ADC chip which is working in the LVDS mode. The data out(D0+,D0-,......D13+ and D13-),along with data clock out(DC0+,DC0-) and out of range(OUR) are connected physically to Sparta 3a dsp. My question is how do I directly collect these LVDS signals in my sparta 3a dsp core. How do I get back my data in aa format I can work on? ------------...


Digitally Controlled Impedance with Lattice ECP2M FPGA's

Started by JSalk in comp.arch.fpga13 years ago 2 replies

Does anyone know if the LATTICE ECP2M FPGA's have on die Digitally Controlled Impedance (DCI) matching for input LVDS? I am designing a x4 lane...

Does anyone know if the LATTICE ECP2M FPGA's have on die Digitally Controlled Impedance (DCI) matching for input LVDS? I am designing a x4 lane PCIe digitiser card with the National 500MSPS ADC and the ECP2M FPGA. The ADC output 32 pair LVDS and I have read the FPGA datasheet but there is no mention of DCI?? Thanks slkjas


connecting Xilinx XUP expansion headers

Started by Alderaan in comp.arch.fpga10 years ago

Hello, I'm having a problem connecting a Xilinx XUP board with an ADC board. The scheme is very simple, from XUP board I send a clock (20MHz) to...

Hello, I'm having a problem connecting a Xilinx XUP board with an ADC board. The scheme is very simple, from XUP board I send a clock (20MHz) to the ADC board that sends back 16bit parallel samples and a clock (20MHz). These signals (1.8V) enter to the low speed connector of the Xup board. The cable I chosed for the connection between boards is an ATA-133 cable. Actually, that cable is ca...


Analog to Digital Converted (ADC) & Spartan 3

Started by Herb T in comp.arch.fpga14 years ago 4 replies

Greetings, I am looking at an application that will provide an analog input signal in the 125 to 500 KHz frequency range, and wanted to convert...

Greetings, I am looking at an application that will provide an analog input signal in the 125 to 500 KHz frequency range, and wanted to convert it to a digital signal that would be processed by a Spartan 3 FPGA. I found two xilinx app notes that address issues related these areas (but based on Virtex FPGA): http://www.xilinx.com/bvdocs/appnotes/xapp155.pdf (Virtex ADC) http://www.xilinx.c...


Data Validity and Freshness

Started by Fizzy in comp.arch.fpga13 years ago 1 reply
ADC

Hi all, I am trying to interface a ADC with FPGA through SPI interface. FPGA will have SPI slave implemmented. Once i receive the data from...

Hi all, I am trying to interface a ADC with FPGA through SPI interface. FPGA will have SPI slave implemmented. Once i receive the data from ADC i am required to have some kind of data validity and freshness check. One way to check validity is to have data parity embedded with data but ARE THERE ANY OTHER OPTIONS because parity is prone to bit(s) error. Also i am required to have some logic...


ADC unit with 2 input channels, 12 bit, 10MHz conversion rate, 4Ksamples FIFO, USB (or PCI on PC104+ form) interface, Linux, QNX driver

Started by Anonymous in comp.arch.fpga15 years ago

I'm looking Analog to Digital Converter (ADC) board with 2 Input channels 12 bit resolution 10 Mega saples/second conversion rate ...

I'm looking Analog to Digital Converter (ADC) board with 2 Input channels 12 bit resolution 10 Mega saples/second conversion rate 4 K samples buffer USB interface (or PCI on PC104+ form) Linux and QNX (and Windows) SW drivers Does anybody recomment any board with above characteristics? Thx


ADC Interleaving

Started by maxascent in comp.arch.fpga13 years ago 4 replies
ADC

I am considering trying to interleave two 250MS/s ADCs. Would this be a good idea? possible? or too much trouble? Cheers Jon

I am considering trying to interleave two 250MS/s ADCs. Would this be a good idea? possible? or too much trouble? Cheers Jon


ADC implementation on FPGA ?

Started by Scope in comp.arch.fpga13 years ago 8 replies

Hi ! I would know if , to your mind, it may be possible to implement a 16 bits Analog-to-Digital Converter on a FPGA ( like a Spartan 3 for...

Hi ! I would know if , to your mind, it may be possible to implement a 16 bits Analog-to-Digital Converter on a FPGA ( like a Spartan 3 for example ... ) . Any idea is welcome. Thanks.


System Generator problem with XtremeDSP

Started by Tonny in comp.arch.fpga15 years ago
ADC

Hello, I want know if it is possible co-simulate with hardware-in-loop the xtremedsp kit II, if I use ADC and DAC. Always that I try...

Hello, I want know if it is possible co-simulate with hardware-in-loop the xtremedsp kit II, if I use ADC and DAC. Always that I try genarate, the program make error. Tonny


driving high speed ADC using an FPGA

Started by Sanka Piyaratna in comp.arch.fpga13 years ago 4 replies
ADC

Hi Everyone, I am wondering if it would be possible to drive a 800 MHz 10 bit parellel A/D using an FPGA which has a 100MHz system...

Hi Everyone, I am wondering if it would be possible to drive a 800 MHz 10 bit parellel A/D using an FPGA which has a 100MHz system clock. Thanks, Sanka


FPGA with ARM+CAN+USB+ethernet+ADC

Started by Antti in comp.arch.fpga12 years ago 4 replies

http://www.zylogic.com.cn/english/products04.htm I wonder what that is? it looks like the product Triscend never announced, but maybe its...

http://www.zylogic.com.cn/english/products04.htm I wonder what that is? it looks like the product Triscend never announced, but maybe its a hoax, still funny at least the spec are known now what Triscend was about to announce just before it was purchased by Xilinx Antti


Sigma-Delta A/D

Started by Marco in comp.arch.fpga14 years ago 20 replies
ADC

Hallo, is there anybody who can help me to find out the scheme of a 16-bit delta-sigma adc? I have already made some searches into google...

Hallo, is there anybody who can help me to find out the scheme of a 16-bit delta-sigma adc? I have already made some searches into google but I don't have found interesting informations. Many Thanks Marco Toschi


Are FPGAs available with ADCs onchip ?

Started by Jay in comp.arch.fpga13 years ago 2 replies
ADC

Hi, Could anybody tell me whether any manufacturer of FPGAs provide onchip ADC ? Regards jay

Hi, Could anybody tell me whether any manufacturer of FPGAs provide onchip ADC ? Regards jay


Re: ADC implementation on fpga? Information and procudures wanted.

Started by pingboypulsar<spamoff>@hotmail.com in comp.arch.fpga14 years ago 4 replies

Thanks! Yeah the problem is im a chemical engineer doing research with very basic electronic engineering knowledge. I need a kick in the...

Thanks! Yeah the problem is im a chemical engineer doing research with very basic electronic engineering knowledge. I need a kick in the right direction. There is alot of stuff out there, i just need to figure out the right path. Current help and more is very much appreciated! Cheers! -- ---------------------------------------------- Posted with NewsLeecher v3.0 Final * Binar...


Bidirectional Pin FPGA (Parallel ADC)

Started by Anonymous in comp.arch.fpga5 years ago 9 replies

Hey guys(and gals) FPGA convert here trying to use bidirectional pins on an Altera Board within a data acquisition project. What are the ways...

Hey guys(and gals) FPGA convert here trying to use bidirectional pins on an Altera Board within a data acquisition project. What are the ways to implement such a design in VHDL or Verilog? Thanks! Olu


DDC design

Started by Jan in comp.arch.fpga16 years ago 2 replies

Hi, Can anyone point me at a vhdl design for a DDC, Digital Down Convertor, in an FPGA. Preferably free. It should be a wideband design with...

Hi, Can anyone point me at a vhdl design for a DDC, Digital Down Convertor, in an FPGA. Preferably free. It should be a wideband design with up to 10MHz and as low as 100KHz bandwidth. Resolution of adc is 14bits. Also it should be possible to synthesise it with the Xilinx Webpack. Thanks for any help Jan


Gain and Offset Correction

Started by Marco T. in comp.arch.fpga12 years ago 4 replies

Hallo, do you know a way to perform gain and offset correction of the adc output in vhdl? Many Thanks Marco T.

Hallo, do you know a way to perform gain and offset correction of the adc output in vhdl? Many Thanks Marco T.


Actel Fusion FPGA

Started by Rehman in comp.arch.fpga12 years ago 3 replies

Hello, I am working on Actel Fusion FPGA. I am having problems with the ADC in my design. Can someone please help me with this? Thanks...

Hello, I am working on Actel Fusion FPGA. I am having problems with the ADC in my design. Can someone please help me with this? Thanks alot! Cheers!


Actel Fusion?

Started by MikeD in comp.arch.fpga13 years ago 2 replies

Has anyone here had any experiance with the Actel Fusion FPGAs? I saw a couple of posts asking this about 6 months ago, but no one had hardware...

Has anyone here had any experiance with the Actel Fusion FPGAs? I saw a couple of posts asking this about 6 months ago, but no one had hardware yet. Did they finally start shipping their demo boards? Is this true programable analog, with filtering/amplification/etc, or is it just an analog mux to an ADC? Thanks, Mike


Looking for a development board

Started by Alfreeeeed in comp.arch.fpga12 years ago 8 replies

Hi everybody , I am looking for a development board. My intention is to devolp a DSP application so ideally should contain...

Hi everybody , I am looking for a development board. My intention is to devolp a DSP application so ideally should contain : -xc3s500e-pq208 -ADC