Virtex 4 FX12 minimodule

Started by bhatti in comp.arch.fpga9 years ago 1 reply

Hi all Has any one used Virtex 4 FX12 minimodule along with any ADC(analog to digital converter) IC for sending digitiized data on...

Hi all Has any one used Virtex 4 FX12 minimodule along with any ADC(analog to digital converter) IC for sending digitiized data on ethernet? If someone has any experience on FX12 mini module kindly share it. THANKS --------------------------------------- Posted through http://www.FPGARelated.com


SBC with ADC, 1GE, and SATA2?

Started by Mike McDonald in comp.arch.fpga11 years ago 2 replies

I'm lokking for a small (4x6", 6x8", range) SBC that has a reasonably good A/D converter (100+MSPS), at least one 1G ethernet, and one or more...

I'm lokking for a small (4x6", 6x8", range) SBC that has a reasonably good A/D converter (100+MSPS), at least one 1G ethernet, and one or more SATA-2 ports. I'm not picky about the processor. Anything that runs Linux or an FPGA would be fine. A nice option would be an LCD and keypad interface. Has anyone got any recommendations? All of my Google queries are possessed! I keep getting the s...


Seeding random number generator

Started by Anonymous in comp.arch.fpga10 years ago 3 replies

Sorry if this has been covered already. I am developing a testbench for a design and I want the behavioral models for external devices to use...

Sorry if this has been covered already. I am developing a testbench for a design and I want the behavioral models for external devices to use random parameters within the constraints of the data sheets. I figured out how to start up a sim with a seed variable in Modelsim, but now I'm confused about how to use that seed. Say I have two processes, each controlling one aspect of an ADC. Does eac...


equivalent time sampling

Started by maxascent in comp.arch.fpga14 years ago 10 replies
ADC

I am designing a data aqu system using an fpga and adc sampling at 250MHz. I want to use equivalent time sampling to increase the sampling rate to...

I am designing a data aqu system using an fpga and adc sampling at 250MHz. I want to use equivalent time sampling to increase the sampling rate to a few GHz for repetative signals. I am not sure how to go about implementing it though. Any info would be welcome, thanks. Jon


FPGA Selection Question

Started by maxascent in comp.arch.fpga13 years ago 6 replies

Hi I am using a 8-bit ADC with parallel LVDS outputs clocked at 250MHz. I want to interface this to a FPGA, then place the samples into a...

Hi I am using a 8-bit ADC with parallel LVDS outputs clocked at 250MHz. I want to interface this to a FPGA, then place the samples into a DDR memory. Then send the samples from memory via ethernet to a PC. Can you recommend an FPGA from either Xilinx or Altera to do the job. Thanks Jon


getting samples from an RF board onto the system

Started by vits in comp.arch.fpga11 years ago 1 reply
ADC

hi, I have got an RF board (antenna+ADC+Some signal processing boxes on a board). The output is a 2bit data and a clock (16MHz). I need to...

hi, I have got an RF board (antenna+ADC+Some signal processing boxes on a board). The output is a 2bit data and a clock (16MHz). I need to store this 2 bit data for 1 second onto my system in some text or binary format for using it in my simulations. What is the best (in very less time) method to do this? Any ideas Thanks, Vittal


DSP-PC architectural advice needed.

Started by soos in comp.arch.fpga14 years ago 4 replies

Hello, I have an idea for a design of a data aquisition system and i am willing to verify the possibility to implement it. Basically it's...

Hello, I have an idea for a design of a data aquisition system and i am willing to verify the possibility to implement it. Basically it's an ADC connected to the TS201 that sends the entire information sampled to a PC through one of it's LVDS connectors. On the PC there is a PCI Card that knows how to do LVDS for example the PCI GP-ECL/SSD16. of the EDT group. Before checking all the car...


Calculating SFDR in FPGA

Started by Mile in comp.arch.fpga9 years ago 2 replies

Hello All, I am new in this forum. I would like to ask if there is a way to calculate the SFDR in FPGA. I have limited resources in the...

Hello All, I am new in this forum. I would like to ask if there is a way to calculate the SFDR in FPGA. I have limited resources in the FPGA, so calculating the FFT is not so preferable. knowing that my bandwidth is around 1.5 GHz. my main goal is to evaluate the ADC, SFDR specifically. any idea is appreciated. Mile --------------------------------------- ...


Complex Baseband

Started by morpheus in comp.arch.fpga12 years ago 11 replies

Howdy, For FM/AM demod, you require a complex baseband. I am downconverting the IF from 1MHz to baseband by multiplying the input stream (12...

Howdy, For FM/AM demod, you require a complex baseband. I am downconverting the IF from 1MHz to baseband by multiplying the input stream (12 bits) from the ADC with Sin and Cosine outputs of a DDS and therefore, generating I, Q I am using standard 18x18 signed multipliers in Xilinx to do the mixing. Is this right or should I use a complex multiplier? The reason why I am asking this question...


Re: ADC implementation on fpga? Information and procudures wanted.

Started by pingboypulsar<spamoff>@hotmail.com in comp.arch.fpga14 years ago 1 reply

Basically its for industrial sensors, like thermocouples, 0-10v, -5v-5v, 0-5v, 0-20ma, 4-20ma sensors. --...

Basically its for industrial sensors, like thermocouples, 0-10v, -5v-5v, 0-5v, 0-20ma, 4-20ma sensors. -- ---------------------------------------------- Posted with NewsLeecher v3.0 Final * Binary Usenet Leeching Made Easy * http://www.newsleecher.com/?usenet ----------------------------------------------


Re: ADC implementation on fpga? Information and procudures wanted.

Started by pingboypulsar<spamoff>@hotmail.com in comp.arch.fpga14 years ago 2 replies

thanks for that info. So what is the best approach to learning how to do this? Is it possible to elaborate a bit more on this "..so...

thanks for that info. So what is the best approach to learning how to do this? Is it possible to elaborate a bit more on this "..so 2Gsps@8bits fans-out to 500Msps@32bits, where it can (just) feed into a FPGA..." Cheers! -- ---------------------------------------------- Posted with NewsLeecher v3.0 Final * Binary Usenet Leeching Made Easy * http://www.newsleecher.com/?usenet ---...


Analog FPGAs: how fast?

Started by David M. Palmer in comp.arch.fpga12 years ago

What sorts of frequencies can currently-available analog FPGAs run at? (Either pure analog, or mixed such as the Actel Fusion.) For example,...

What sorts of frequencies can currently-available analog FPGAs run at? (Either pure analog, or mixed such as the Actel Fusion.) For example, if I wanted a gated integrator with a sub-microsecond gating windows, what product lines, if any, can handle that? I know e.g. that the Fusion has a 600 ksample/s ADC with a multiplexer, but I don't know the bandwidth of the amplifiers etc. in the an...


Video - DSP Eval board with Altera

Started by homoalteraiensis in comp.arch.fpga13 years ago 3 replies

Is there anybody out having experiences with an evaluation board, containing an Altera FPGA like Cyclone or Stratix and doing Video processing...

Is there anybody out having experiences with an evaluation board, containing an Altera FPGA like Cyclone or Stratix and doing Video processing with it? Can anybody recoomend a certain board with a good analog behaviour (high dynamic ADC) - possibly with a (hard) DSP? Thanks in advance.


Conceptos about VCCINT,VCCAUX,etc

Started by jajo in comp.arch.fpga12 years ago 1 reply
ADC

Hi!, Maybe this doubt is stupid but nobody has explained it to me so could you help me? What are the functionality of the listed elements...

Hi!, Maybe this doubt is stupid but nobody has explained it to me so could you help me? What are the functionality of the listed elements into the FPGA? Why are there several of them into the FPGA?: -VCCINT -VCCAUX -VCCO -VBATT -MGT VREF -MGT CLK -MGT Termination Reference -System Monitor/ADC Thanx Jajo


Interfacing Cyclone III to 3.3v LVDS devices

Started by liqi...@gmail.com in comp.arch.fpga12 years ago 3 replies

How can i interface the cyclone III with 2.5v LVDS to 3.3v LVDS adc & dac ? Thanks

How can i interface the cyclone III with 2.5v LVDS to 3.3v LVDS adc & dac ? Thanks


How to port simulink design to FPGA?

Started by Bryan in comp.arch.fpga12 years ago

Hi, I have a design where I have implemented a simple band pass filter found to be working even on hardware in the loop cosimulation. Now i have...

Hi, I have a design where I have implemented a simple band pass filter found to be working even on hardware in the loop cosimulation. Now i have a problem since i am pretty new to simulink, I do not know how am i suppose to port this design into the XTREME DSP development kit IV. I know i need to use the ADC and DAC blocks in the design but not sure where to put it or what steps to take....


Double buffering

Started by dh2006 in comp.arch.fpga13 years ago 3 replies

I've read much about Double Buffering, especially that it is good practice (on Xilinx devices) to double buffer data signals (such as...

I've read much about Double Buffering, especially that it is good practice (on Xilinx devices) to double buffer data signals (such as ADC inputs), and place the double buffer in the IOB associated with the pin. Can someone explain to me, what double buffering is and why you would use it? Any links to reference information would be appreciated. Many thanks.


50 MSPS ADC with Spartan 3 FPGA - clock issues

Started by Anonymous in comp.arch.fpga13 years ago 12 replies

Hello, I'm in the middle of a project which involves digitizing and decoding baseband NTSC composite video. Right off the top, I'll let...

Hello, I'm in the middle of a project which involves digitizing and decoding baseband NTSC composite video. Right off the top, I'll let everybody know that this is part of an educational project (part of it for a university project, though it's largely a hobbyist type project). I realize that the project will be useless in a couple years, and that there are pre-made devices out there, but ...


adaptive filter FPGA

Started by cutemonster in comp.arch.fpga12 years ago 12 replies

thanks for looking and please help me. I have a 16 bit ADC sampling at 50Mhz. I take only 10 MSB and display it in my video 1024 x 768 as an...

thanks for looking and please help me. I have a 16 bit ADC sampling at 50Mhz. I take only 10 MSB and display it in my video 1024 x 768 as an output to check the signal. I see a continuous line displayed in my monitor which still toggle within 1 or 2 pixels. My question is, do I need a adaptive filter to really smooth the line in only 1 pixel wide? To make my question clear, for example wh...


FPGA

Started by ECS.MSc.SOC in comp.arch.fpga8 years ago 2 replies

Hi all I want to do a project with a FPGA. The FPGA that I choos is ALTERA Cyclone III.I think that there is no analog input in that. Of...

Hi all I want to do a project with a FPGA. The FPGA that I choos is ALTERA Cyclone III.I think that there is no analog input in that. Of course, I know that I can use an external ADC(A/D) but I cannot do it because my inputs and outputs are too much. can everyone tell me a FPGA from this family (ALTERA) that have analog inputs and output? Regards