i2c,ahb,apb

Started by vits in comp.arch.fpga11 years ago 7 replies

Hi, I came across these buses i2c ,ahb,apb.What is the difference between them. I dont know about the ahb or apb .just started reading about...

Hi, I came across these buses i2c ,ahb,apb.What is the difference between them. I dont know about the ahb or apb .just started reading about i2c. I have to test the i2c bus in verilog. In i2c bus DUT(design under test) i saw something like wishbone interface or ahb thing.what does it mean .please explain me in detail. or give some links.I am exploring them too. Thanks, Vittal


Adding TDM to ZSP400

Started by praveen in comp.arch.fpga13 years ago
AHB

Hello, ZSP IP core doesnot contain TDM. Can some one tell how can i include TDM to it, i like you need to have a master AHB bridge and a slave...

Hello, ZSP IP core doesnot contain TDM. Can some one tell how can i include TDM to it, i like you need to have a master AHB bridge and a slave AHB bridge and connect TDM to master AHB bridge. So if anyone has any information about it, please share it with me. Thanks and regards Praveen


AHB and APB master VHDL generator

Started by beky...@gmail.com in comp.arch.fpga9 years ago 2 replies

This project demonstrates an easy way to create AMBA masters and slaves. It includes an AHB master, AHB slave, APB master and...

This project demonstrates an easy way to create AMBA masters and slaves. It includes an AHB master, AHB slave, APB master and APB slave. http://bknpk.no-ip.biz/LEON/AHB_APB_leon/AHB_APB_leon.html


AHB VHDL code

Started by praveen in comp.arch.fpga13 years ago 1 reply

Hello, 1.Can anyone provide me with some AMBA AHB VHDL models?or is there anyone who has designed one? 2. What is role played by...

Hello, 1.Can anyone provide me with some AMBA AHB VHDL models?or is there anyone who has designed one? 2. What is role played by wrapper??? Thanks and regards Praveen


USB interface With AMBA AHB

Started by Joe in comp.arch.fpga12 years ago 11 replies

Hi Folks, Any inputs regarding interfacing USB1.1 with ARM Core(7TDMI) using AMBA AHB/APB 2.0 Specification?? Your help will be...

Hi Folks, Any inputs regarding interfacing USB1.1 with ARM Core(7TDMI) using AMBA AHB/APB 2.0 Specification?? Your help will be greatly appreciated.


USB and AHB

Started by terabits in comp.arch.fpga11 years ago 7 replies

Hi I am very new to usb, I have some basic questions reagarding usb with ahb . Suppose i have a ahb structure like 2 masters and 2...

Hi I am very new to usb, I have some basic questions reagarding usb with ahb . Suppose i have a ahb structure like 2 masters and 2 slaves. i want to have 2usb devices .....will this usb (usb 2.0 device) sit on the slave side ? what will be on the master side ? suppose one dma as a master i have will the another master be arm processor or can it be some other usb device ? if so what cou...


DDR SDRAM interface working with AMBA-AHB

Started by Anonymous in comp.arch.fpga12 years ago 1 reply

Hi folks, I'm trying to get a DDR-SDRAM controller work as an AHB slave. According to the transfer timings in the AMBA Spec. Rev. 2, the...

Hi folks, I'm trying to get a DDR-SDRAM controller work as an AHB slave. According to the transfer timings in the AMBA Spec. Rev. 2, the next transfer can't go on until the slave involved in the previous transfer sets the HREADY signal. That means each time a read transfer associated with the DDR is initiated, AHB masters have to wait until the DDR finishes the read burst and puts ...


AHB VHDL code

Started by praveen in comp.arch.fpga13 years ago

Thanks Etem Tezcan, I am looking for some reference code of AHB. Can some one please give some reference where i can find it. Thanks and...

Thanks Etem Tezcan, I am looking for some reference code of AHB. Can some one please give some reference where i can find it. Thanks and regards Praveen


AMBA AHB

Started by mack in comp.arch.fpga13 years ago 3 replies
AHB

Hi, I am designing an AMBA-AHB Master interface.As per the spec ,there is a delayed version of the HMASTER bus is used to control the...

Hi, I am designing an AMBA-AHB Master interface.As per the spec ,there is a delayed version of the HMASTER bus is used to control the write data mux.So my doubt is ,whether I should have one clk delayed hwdata from haddr or both can be driven at the same time..It's pretty urgent to make up the decision... ~~Kumar.


AHB_SLAVE

Started by mack in comp.arch.fpga13 years ago
AHB

Hi, According to AHB protocol ,will the AHB-Slave gives retry only for the first non-seq address from the Master(like my doubt is,can...

Hi, According to AHB protocol ,will the AHB-Slave gives retry only for the first non-seq address from the Master(like my doubt is,can the Slave issue a RETRY even in the middle of a burst of transfer)..Please reply me soon..I am in the middle of my design and i need to take care of this issue....it's pretty urgent... Regards, Mack


AHB master related

Started by san in comp.arch.fpga13 years ago 1 reply

question asked to arm on 22/12/2004 ----------------------------------- my questions are: 1) when the master on AHB bus is getting ready signal...

question asked to arm on 22/12/2004 ----------------------------------- my questions are: 1) when the master on AHB bus is getting ready signal low from slave then is there any way the master start a new transaction on the bus. Also if slave give the error response after some predefined number of cycle to release the bus then is it a correct approach or is there any better approach to relea...


PLB to AMBA AHB bus bridge

Started by Mariem Makni in comp.arch.fpga3 years ago
AHB

Hi everybody, I want to know if there is an opensource PLB to AMBA AHB Bridge? Thanks. regards,

Hi everybody, I want to know if there is an opensource PLB to AMBA AHB Bridge? Thanks. regards,


Strange FPGA problem

Started by Anonymous in comp.arch.fpga12 years ago 1 reply
AHB

Hello Guys, I am working on some verfication of the SoC IP. To verify these IP we are implementing it on FPGA. I am facing an strange...

Hello Guys, I am working on some verfication of the SoC IP. To verify these IP we are implementing it on FPGA. I am facing an strange problem. One of the IP which i have implemented as Master and slave AHB interface. Since the AMBA interface i am having is a multiplexed bus i need to multiplex the master and slave interface signal. So to do that i am using grant signal of AHB to multip...


AHB-Slave

Started by mack in comp.arch.fpga13 years ago 1 reply
AHB

Hi, When the current AHB slave is busy (hready low) servicing the Master,but if the master drives IDLE transfer in the next cycle ,...

Hi, When the current AHB slave is busy (hready low) servicing the Master,but if the master drives IDLE transfer in the next cycle , then according to the protocol slave should give a zero wait state OKAY response,but by seeing the hready high for this IDLE response ,master will drive it's address and data.Later the slave will drive hready for the pending(previous transfer) service.This is ...


how to interface a ddr2 memory controller to a processor

Started by rana in comp.arch.fpga7 years ago 4 replies
AHB

hi all, i have a ddr2 controller that works on 4 burst mode. ddr2 dq width is 16. i must provide 2, 32 bit data to the controller before...

hi all, i have a ddr2 controller that works on 4 burst mode. ddr2 dq width is 16. i must provide 2, 32 bit data to the controller before writing it to memory. As well as when reading from a memory location it gives out 2, 32 bit data out. my processor is a master AHB, has a 32 bit address and 32 bit data bus. How can i connect these 2 together? problem is ahb sends out 32 bit data but i ...


CoreABC from Microsemi

Started by alb in comp.arch.fpga4 years ago

Hi everyone, I'm currently laying down the architecture of an FPGA which is the main controller for a set of mechanisms and we wanted to...

Hi everyone, I'm currently laying down the architecture of an FPGA which is the main controller for a set of mechanisms and we wanted to profit of an amba ahb to interconnect various elements [1], included a slightly modified microblaze core (MB) with an additional floating point unit. The system does need to have an overall controller/sequencer or whatever you want to call it in ord...


example for excalibur epxa1

Started by zhangdidi in comp.arch.fpga13 years ago

Hello, does anyone have an example for a circuit using an AMBA bus on the excalibur epxa1? I built a circuit with the following components: a...

Hello, does anyone have an example for a circuit using an AMBA bus on the excalibur epxa1? I built a circuit with the following components: a arm processor, a stripe_pld_master, a user interface ahb slave and a logic block in FPGA. But it does not work. I want to have an example to have a comparison and to see, where the problem in my circuit lies. Thanks! Diandian


Checking the PCI master implemented in FPGA

Started by Anonymous in comp.arch.fpga12 years ago

Hi All, I have implemented a AHB-PCI IP in the virtex2pro FPGA. While accessing through ARM JTAG AMBA side is okay , but PCI is not working. I...

Hi All, I have implemented a AHB-PCI IP in the virtex2pro FPGA. While accessing through ARM JTAG AMBA side is okay , but PCI is not working. I basically want to know what are the basic steps to check the PCI interface . Is there any specific procedure or checklist ? Waiting for your reply Thanks and regards Praveen


can't trap custom ITon NIOS

Started by Julien Chevalier in comp.arch.fpga13 years ago 2 replies

Hello, I use quartus II 4.00 and SOPC builder 4.00 to build a NIOS system on a Stratix II board. I enabled the support for external...

Hello, I use quartus II 4.00 and SOPC builder 4.00 to build a NIOS system on a Stratix II board. I enabled the support for external interruptions, add a user defined IP connected via the provided avalon ahb bridge. Everything is ok. Then I try to use the interruption of the bridge, everything on the wire is ok until the data_master_irq gets high. The iq number is ok, NIOS makes a cou...


Maximum Operating Frequency

Started by terabits in comp.arch.fpga11 years ago 1 reply
AHB

Hi On what factors the maximum operating frequency of ahb master and slave depends ? in general what is the maximum frequency we can go for...

Hi On what factors the maximum operating frequency of ahb master and slave depends ? in general what is the maximum frequency we can go for ? regards