ANN: Confluence 0.6

Started by Tom Hawkins in comp.arch.fpga14 years ago

Confluence is a functional programming language for digital logic design (FPGA/ASIC), real-time embedded software development, and DSP...

Confluence is a functional programming language for digital logic design (FPGA/ASIC), real-time embedded software development, and DSP modeling. Confluence source code compiles into Verilog, VHDL, C, and Python for synthesis, implementation, and verification. The release of Confluence 0.6 features many language and compiler improvements including simplified syntax, static connection ana...


Q: Xilinx PROM file generation

Started by Gerald Weile in comp.arch.fpga14 years ago 1 reply

Hello, is there any way to create a PROM programming file that contains not only Xilinx BIT files but also a Lattice BIT file ? Best...

Hello, is there any way to create a PROM programming file that contains not only Xilinx BIT files but also a Lattice BIT file ? Best regards, Gerald -- --------------------------------------------------- Gerald Weile mailto:GWE@msc-ge.com MSC Vertriebs GmbH Phone:+49-7249-910-186 Fax: -268 ASIC Design http://www.msc-ge.com


Time Killing Post P&R Simulation

Started by Nagaraj in comp.arch.fpga14 years ago 6 replies

Hi, I have a moderately big design (~250K equivalent ASIC gates) in Vertex FPGA. The post place & route simulation in Modelsim takes...

Hi, I have a moderately big design (~250K equivalent ASIC gates) in Vertex FPGA. The post place & route simulation in Modelsim takes hours together for simulating about 2-3 ms of input data. This is a time killing step in my product development lifecycle. Moreover if some timing errors occur (evenafter analyzing P&R static timing) more syn-map-par-sim iterations are required with modifie...


ASIC/FPGA programming

Started by Julien Sobrier in comp.arch.fpga14 years ago 1 reply

Hello I've done some work in ASIC Verilog design, but not that much in FPGA design. SO, I wonder what are the mani differences between these 2...

Hello I've done some work in ASIC Verilog design, but not that much in FPGA design. SO, I wonder what are the mani differences between these 2 types od design. I found a multimedia document about this on Xilinxs website, but I cannot read it on my Linux box. Do you know a web site which could give me a brief overview of the most important differences? By the way, I thought it was possi...


Internship/Co-op

Started by KaRtiK in comp.arch.fpga14 years ago

Hello I had posted once before in July Sorry to spam the group again. I am looking for an internship/Co-op for Spring 2004 in the field...

Hello I had posted once before in July Sorry to spam the group again. I am looking for an internship/Co-op for Spring 2004 in the field of FPGA /ASIC design, computer architecture design. I am a grad student in Comp Engg at UW-Madison. Over the last 5 months I have designed completely in Verilog 2 ARM cores.(a super scalar version and a basic 5 stage pipelined ARM core) as part of ...


Does a dont_use statement exist?

Started by kris in comp.arch.fpga14 years ago

Hi guys, Is it possible to somehow put a synthesis constraint (preferably with a flag or with directly in the verilog netlist and otherwise...

Hi guys, Is it possible to somehow put a synthesis constraint (preferably with a flag or with directly in the verilog netlist and otherwise in the synthesis constraint file) such that the MUXes from the slices (e.g. MUXF5) are not used, but instead all logic is mapped directly onto the LUT's without these Muxes? Like for example for an asic design you can tell to synopsys to not use ce...


ASIC speed

Started by Yu Jun in comp.arch.fpga14 years ago 4 replies

I'm working on a cpu core and intend to embed it into ASIC circuits, with the aim to do some network processing. Now the FPGA prototype...

I'm working on a cpu core and intend to embed it into ASIC circuits, with the aim to do some network processing. Now the FPGA prototype is running and a 66M speed is achieved( xilinx virtexII-4 ). Wondering how fast it can run in ASIC, we had our ASIC guys to synthesize the codes and the result was shocking, it reached 400M! Far beyond our expectation of 150M. The library we used was of 0.13u...


ASIC vs FPGA

Started by newbie in comp.arch.fpga14 years ago 2 replies

Hi all Can someone help in understanding the main difference between ASIC and FPGA. I keep hearing both these terms and am not fully...

Hi all Can someone help in understanding the main difference between ASIC and FPGA. I keep hearing both these terms and am not fully clear. Is there a website explaning this? Thanks


FPGA Device Utilization

Started by Sudip Saha in comp.arch.fpga14 years ago

Hi All, I am looking for documentation on estimation of FPGA device utilization from a high level design specification(idea). Can...

Hi All, I am looking for documentation on estimation of FPGA device utilization from a high level design specification(idea). Can anybody tell me where I can find out this kind of document which gives idea about how to do rough estimate of gate count(ASIC) or device utilization from a high level design description. The design will ofcourse be made in VHDL/Verilog.


Tool for connecting modules,download free,quick demo

Started by Song in comp.arch.fpga14 years ago

Topweaver v2.0 A GUI-based tool for connecting HDL modules, also called structural integration. You can use it in ASIC, FPGA or CPLD...

Topweaver v2.0 A GUI-based tool for connecting HDL modules, also called structural integration. You can use it in ASIC, FPGA or CPLD designs. FEATURES Extract ports from cell modules automatically Full mixed Verilog, Verilog 2001 and VHDL supported Automatically language recognition Connect ports in graph interface Great visual aid while connecting Sma...


Position: custom mixed-signal Application Specific Integrated Circuits (ASIC's).

Started by news in comp.arch.fpga14 years ago

A friend sent this to me and asked to pass it around. -- rk From: http://www.nasajobs.nasa.gov/search/searchaction.cfm Vacancy...

A friend sent this to me and asked to pass it around. -- rk From: http://www.nasajobs.nasa.gov/search/searchaction.cfm Vacancy Announcement Number: GS04D0022 - Goddard Space Flight Center Position: Electronics Engineer, AST Electronic Instrumentation System, GS- 0855-15 Goddard Space Flight Center Vacancy Announcement Number: GS04D0022 Opening Date: 11/05/2003 Closing Date: ...


From ASIC to FPGA these days

Started by avalanche effect in comp.arch.fpga14 years ago 5 replies

Googling web & usenet didn't provide answer or pointers - so here it goes: We have a fully tested design on fat Xilinx FPGA. Must go to...

Googling web & usenet didn't provide answer or pointers - so here it goes: We have a fully tested design on fat Xilinx FPGA. Must go to ASIC, 0.18 or better. Relatively simple design, 3 clock domains, 300K gates. The only interface is USB, so very low pin count. If the foundry doesn't have USB phy in standard lib, we'll interface external phy. The question is - how long does it take - ho...


Parallel Cable 4 & Linux

Started by Rudolf Usselmann in comp.arch.fpga14 years ago 8 replies

I just found out that ISE 6.1 for Linux does not support the Parallel Cable 4 (both products from Xilinx ! ). Does anybody know of a tools...

I just found out that ISE 6.1 for Linux does not support the Parallel Cable 4 (both products from Xilinx ! ). Does anybody know of a tools that will allow me to use the Parallel Cable 4 under Linux ? (All I need is JTAG download and verify). Thanks, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: ...


Complicated clocking in an FPGA.

Started by A Day & A Knight in comp.arch.fpga14 years ago 2 replies

Hi, there: I have ASIC source codes from a previous communication chip. It has some 23 clocks, many of them are derived from a 144MHz clock...

Hi, there: I have ASIC source codes from a previous communication chip. It has some 23 clocks, many of them are derived from a 144MHz clock (72/36/24/18/.../2/1MHz), only three from other sources. The ASIC codes made use of a clock generator with clock gating... How am I going to handle all these different clocks? In a Vertex chip, there is only 16 clock buffers. May I use a "always...


is this a good idea

Started by Paul in comp.arch.fpga14 years ago 7 replies

Hi I know that the "reg"'s are all zeroes when powered on (on Xilinx FPGAs). Is this a good idea (assumption) to work on? Can I assume...

Hi I know that the "reg"'s are all zeroes when powered on (on Xilinx FPGAs). Is this a good idea (assumption) to work on? Can I assume the same for ASIC development? that is I don't have to change my codes later on? Thanks.


DCM Synthesis - Certify Planner Error

Started by Lagudu Sateesh in comp.arch.fpga14 years ago

Hello!!! I am using DCM component (which is a ISE6.1 coregen synthesizable module) in top level entity. This top level entity is to be...

Hello!!! I am using DCM component (which is a ISE6.1 coregen synthesizable module) in top level entity. This top level entity is to be ASIC prototyped using Certify tool. During certify flow, compilation and estimation of the flow is running smooth with out any errors. During partitioning process, i assigned the DCM component and unassigned nets ( which are in 'system unassigned bin' of Pa...


Is the P&R processing time proportional to the FPGA gate count or the size of my logic?

Started by Kelv...@ SG in comp.arch.fpga14 years ago 3 replies

Hi, there: I am performing active-module P&R for partial reconfiguration. My fixed logic is 30K (ASIC) gates, and the variable logic modules...

Hi, there: I am performing active-module P&R for partial reconfiguration. My fixed logic is 30K (ASIC) gates, and the variable logic modules are 0.5 & 2K gates only...Now I am P&R the variable modules with a blackbox for fixed module, how come it takes over 30 minutes but still ISE 6.1 couldn't finish this small module. I want to know whether the P&R time is more related to my chip size...


10GbE MACs

Started by Robert Sefton in comp.arch.fpga13 years ago

Shopping for an 802.3ae MAC core. I've identified the following vendors so far who seem to have real cores available in verilog rtl (VHDL not...

Shopping for an 802.3ae MAC core. I've identified the following vendors so far who seem to have real cores available in verilog rtl (VHDL not an option): Mentor Cadence MorethanIP GDA Technologies Sistolic For anyone interested, Paxonet and NoBug Consulting have VHDL MACs. This is for an ASIC project but may also involve an FPGA prototype. Has anyone used any of these cores? I'm pa...


asic vs fpga comparison issues

Started by paraag in comp.arch.fpga13 years ago 1 reply

Hi How do i compare asic power/timing features for the same design with an FPGA having that same design....i mean what tecnology does...

Hi How do i compare asic power/timing features for the same design with an FPGA having that same design....i mean what tecnology does xilinx use to fabricate their die , The Xpower readings from the ISE foundation gives an estimate of power , but i would like to know with which asic flow is this power comparable ultimately leading to a hybrid chip ( if it was possible) thanks Paraag ...


FPGA/ASIC design full time job wanted

Started by KaRtiK in comp.arch.fpga13 years ago

Hello I am a Computer Engineering graduate student at the University of Wisconsin - Madison. I specialize in the area of FPGA/ASIC and VLSI...

Hello I am a Computer Engineering graduate student at the University of Wisconsin - Madison. I specialize in the area of FPGA/ASIC and VLSI systems design. I am highly interested in working Full time from Fall 2004. Currently I am working on a co-op at GE Medical systems designing embedded systems for their testing equipment.I am also a research assistant at the VLSI - EDA labs UW M...