how to speed up my accumulator ??

Started by Moti Cohen in comp.arch.fpga16 years ago 40 replies

Hello all, I've a design that contains a NCO (Numerically controlled oscillator). The NCO consists of a 32'bit accumulator. when i write the...

Hello all, I've a design that contains a NCO (Numerically controlled oscillator). The NCO consists of a 32'bit accumulator. when i write the accumulator straight forward like this - process (clk,resetn) begin if resetn = '0' then accumulator '0'); elsif clk'event and clk ='1' then accumulator


Inferring an accumulator using Verilog on Xilinx Spartan 2e

Started by Y K in comp.arch.fpga17 years ago 4 replies

I need to infer an 8 bit accumulator (acc8) using Verilog on the Xilinx Webpack. The Library guide seems to contain syntax errors. I could not...

I need to infer an 8 bit accumulator (acc8) using Verilog on the Xilinx Webpack. The Library guide seems to contain syntax errors. I could not get the tool to infer a loadable accumulator, no matter how I play around with the implementation. I get an adder using 10 slices, instead of 5 slices I should get when an accumulator is inferred. Does anybody know the solution?


accumulator (again)

Started by jmariano in comp.arch.fpga8 years ago 33 replies

Dear All, I'm not an expert in VHDL, i'm just a curious trying to solve a research problem with an FPGA. I'm using a 32 bit accumulator in...

Dear All, I'm not an expert in VHDL, i'm just a curious trying to solve a research problem with an FPGA. I'm using a 32 bit accumulator in a IP, as part of a SoC project with a microblaze, implemented in a Digilent Spartan-3 SKB ( the FPGA is a Xilinx XC3S200). The code is included at the end of this message. The input is a 32 bit signed integer coded in two's complement and the output...


a question about DDFS

Started by fp in comp.arch.fpga13 years ago 2 replies

Hi, I am implementing a direct digital frequency synthesizer in FPGA. It follows the equation Fo = N * Fs / (2^M) The implementastion...

Hi, I am implementing a direct digital frequency synthesizer in FPGA. It follows the equation Fo = N * Fs / (2^M) The implementastion is done by an M-bit phase accumulator. My question is: if 2^M cannot be divided by N, should the accumulator be cleared to zero when wrapping around? The VHDL code for automatical wrap-around is: process(clk, reset) begin if reset='1' then ...


accessing the phase accumulator in Xilinx DDS 5.0

Started by Gerhard Hoffmann in comp.arch.fpga15 years ago

Hi all, is there a way to access the phase accumulator in Xilinx DDS 5.0? (preferably from VHDL) I'd like to determine the carrier...

Hi all, is there a way to access the phase accumulator in Xilinx DDS 5.0? (preferably from VHDL) I'd like to determine the carrier phase between two modulated signals by phaselocking an NCO on each one and then subtracting the phase accus. Given that there is a great DDS already, I dislike reinventing it just to tap an internal signal. BTW the register interface ...


access to phase accumulator in Xilinx DDS 5.0

Started by Gerhard Hoffmann in comp.arch.fpga15 years ago

Hi all, is there a way to access the phase accumulator in Xilinx DDS 5.0? (preferably from VHDL) I'd like to determine the carrier phase...

Hi all, is there a way to access the phase accumulator in Xilinx DDS 5.0? (preferably from VHDL) I'd like to determine the carrier phase between two modulated signals by phaselocking an NCO on each one and then subtracting the phase accumulators. Given that there is a great DDS already, I dislike reinventing it just to tap an internal signal. BTW the register interface is nice if ...


How to reduce jitter of 30-bit accumulator

Started by Am in comp.arch.fpga14 years ago 3 replies

Hello, I have a 30-bit accumulator in which I use the last bit as my clock out to the design. In the following way: always @(posedge...

Hello, I have a 30-bit accumulator in which I use the last bit as my clock out to the design. In the following way: always @(posedge clk or negedge reset_n) begin if (!reset_n) nco_acc[29:0]


Well Known? Phase Accumulator Trick

Started by rickman in comp.arch.fpga12 years ago 1 reply

I recently read the thread started by Jonathan Bromley, titled "Is this phase accumulator trick well-known???". I am building a DPLL and I will...

I recently read the thread started by Jonathan Bromley, titled "Is this phase accumulator trick well-known???". I am building a DPLL and I will be using this technique. I am using a FIFO to delay data by a fixed time where the data is clocked in and out on variable rate clocks. The two clocks run at the same average rate, the input clock is gapped and the output clock is generated by the P...


Soft core processors: RISC versus stack/accumulator for equal FPGA resources

Started by Anonymous in comp.arch.fpga5 years ago 8 replies

It would appear there are very similar resource needs for either RISC or Stack/Accumulator architectures when both are of the "load/store"...

It would appear there are very similar resource needs for either RISC or Stack/Accumulator architectures when both are of the "load/store" classification. Herein, same multi-port LUT RAM for either RISC register file or dual stacks. And the DSP for multiply and block RAM for main memory. "Load/store" refers to using distinct instructions for moving data between LUT RAM and block RAM. Has som...


increment or decrement one of 16, 16-bit registers

Started by Tim Wescott in comp.arch.fpga3 years ago 22 replies

I've been geeking out on the COSMAC 1802 lately -- it was the first processor that I owned all just for me, and that I wrote programs for (in...

I've been geeking out on the COSMAC 1802 lately -- it was the first processor that I owned all just for me, and that I wrote programs for (in machine code -- not assembly). One of the features of this chip is that while the usual ALU is 8-bit and centered around memory fetches and the accumulator (which they call the 'D' register), there's a 16 x 16-bit register file. Any one of these ...


Re: how to speed up my accumulator ??

Started by Allan Herriman in comp.arch.fpga16 years ago

On Fri, 10 Dec 2004 17:58:47 +1100, Allan Herriman wrote: > The AD9901 is basically an XOR gate with an added frequency >...

On Fri, 10 Dec 2004 17:58:47 +1100, Allan Herriman wrote: > The AD9901 is basically an XOR gate with an added frequency > discriminator. ... and T flip flops on the XOR inputs to ensure 50% duty cycle. Allan


Is this phase accumulator trick well-known???

Started by Jonathan Bromley in comp.arch.fpga12 years ago 45 replies

hi comp.arch.fpga, (accidentally posted to comp.lang.vhdl a few moments ago- sorry) The question - repeated after the explanation - is:...

hi comp.arch.fpga, (accidentally posted to comp.lang.vhdl a few moments ago- sorry) The question - repeated after the explanation - is: here's what I think is a nifty trick; has anyone seen it, or been aware of it, before? I can't believe it's really new. I have been messing around with baud rate generators and suchlike - creating a pulse that's active for one clock period at some r...


Still a Beginner: Accumulator has no reset

Started by Anonymous in comp.arch.fpga12 years ago 3 replies

Xilinx ISE 9.2 and ISE 10.1 I wanted to design a simple correlator which correlates a 15 bit sequence with another sequence of 15 bytes (8 bit...

Xilinx ISE 9.2 and ISE 10.1 I wanted to design a simple correlator which correlates a 15 bit sequence with another sequence of 15 bytes (8 bit signed values = Sample below). I needed to zero the summation result after 15 samples, so I did. But compiler didn't. There is no warning but even the simulator does not seem to notice ACC


Re: Is this phase accumulator trick well-known???

Started by Brian Drummond in comp.arch.fpga12 years ago

On Mon, 09 Feb 2009 19:03:01 +0000, Jonathan Bromley wrote: > let's see what the bug report should look like... > > Dear Xilinx, > ...

On Mon, 09 Feb 2009 19:03:01 +0000, Jonathan Bromley wrote: > let's see what the bug report should look like... > > Dear Xilinx, > XST compiled my code exactly the way I wanted it. > Please fix XST so that it will NOT compile my code. > Yours sincerely, > A. Masochist. > > I don't see Xilinx exactly being flooded with > that kind of case; do


phase noise in NCO

Started by Marc Battyani in comp.arch.fpga17 years ago 9 replies

Hello, I want to make a phase measurement at 100MHz with a NCO at 200+ MHz This NCO will have a 32 bit phase accumulator and a 32 bits phase...

Hello, I want to make a phase measurement at 100MHz with a NCO at 200+ MHz This NCO will have a 32 bit phase accumulator and a 32 bits phase offset. The output will be only one bit. I will use a phase comparator followed by an integrator (digital or analogic if needed). At 100MHz the NCO output will be very very noisy but if I integrate it for a rather long time (10ms) will it have a 0 me...


FPGA multiplier

Started by sutejok in comp.arch.fpga14 years ago 10 replies

from the Xilinx Virtex4 spec: =B7 XtremeDSP=99 Slice - 18x18, two's complement, signed Multiplier - Optional pipeline stages - Built-In...

from the Xilinx Virtex4 spec: =B7 XtremeDSP=99 Slice - 18x18, two's complement, signed Multiplier - Optional pipeline stages - Built-In Accumulator (48-bits) & Adder/Subtracter i'm not too familiar with dsp on fpga - what does it mean when it says 18x18 multiplier? is it a hardware multiplier? is there anywhere i can get informations on and how to use them? something specific to virt...


eliminating a DDS

Started by John Larkin in comp.arch.fpga4 years ago 30 replies

I have a design that will use a DDS synthesizer to generate an internal trigger rate for a pulse generator. The chip will be a ZYNQ 7020....

I have a design that will use a DDS synthesizer to generate an internal trigger rate for a pulse generator. The chip will be a ZYNQ 7020. The required upper frequency limit is maybe 20 MHz. The FPGA will have the usual, 48 bit or so, phase accumulator and sine lookup stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in turn drives an LC lowpass filter and a comparator. Stan...


DDS-Based PLL

Started by Kevin Neilson in comp.arch.fpga16 years ago 11 replies

An alternative using a conventional VCO-based PLL with an FPGA would be to implement most of the PLL as a DDS. The FPGA would have a phase...

An alternative using a conventional VCO-based PLL with an FPGA would be to implement most of the PLL as a DDS. The FPGA would have a phase accumulator and BRAM-based sine LUT and would output a sine to a cheap 8-bit DAC. The output of the DAC would be reconstructed with a simple lowpass (with a simplicity based on the oversampling rate) and then squared with a comparator to make a clock of ...


Interfacing to DDS v5.0 in System Generator

Started by Ira Thorpe in comp.arch.fpga14 years ago

I have a system generator model that utilizes the DDS v4.1 block. I wish to upgrade to the DDS v5.0 block to take advantage of some of the new...

I have a system generator model that utilizes the DDS v4.1 block. I wish to upgrade to the DDS v5.0 block to take advantage of some of the new features. However I have noticed that the interface has changed. My specific application utilizes the phase increment register and a constant phase offset of zero. In my v4.0 design, the accumulator width is set to 32 bits which configures the dat...


How to fix this synthese warnings?

Started by Philipp in comp.arch.fpga16 years ago 3 replies

Hello I have implemented an multiplier in the following way: I always take 4 bits of my first operand and multiply it with the second...

Hello I have implemented an multiplier in the following way: I always take 4 bits of my first operand and multiply it with the second operand. So in every step I generate 4 partial products which have to be added. This sum is stored in the accumulator. In the next clock cycle I take the next 4 bits, multiply it with the second operand, sum up the partial products and add this to my ac...