How good are Actel tools

Started by rickman in comp.arch.fpga8 years ago 7 replies

I know Antti has a lot of experience with Actel, so I expect to hear from him, but I am sure there are others out there with experience of Actel...

I know Antti has a lot of experience with Actel, so I expect to hear from him, but I am sure there are others out there with experience of Actel tools. A customer of mine has told me that he used Actel for a project some 4 or 5 years ago and had a problem with the tools that Actel could not give a fix for. I don't recall how he worked around it and I am sure that particular issue has been f...


FPGA security, Actel down, now Xilinx too?

Started by Antti in comp.arch.fpga6 years ago 4 replies

Hi its maybe not so commonly known that there have been products using Actel s= ecure FPGA's have been cloned already many years ago (readback...

Hi its maybe not so commonly known that there have been products using Actel s= ecure FPGA's have been cloned already many years ago (readback done by dark= engineers at Actel), few month ago a paper was published indicating that P= roAsic3 (and other newest Actel FPGA's) have master key that is known not o= nly inside Actel but also for the dark side outside the company. There is a= t le...


more than 90% occupancy in an Actel FPGA

Started by alessandro basili in comp.arch.fpga11 years ago 6 replies

Hi to everyone, I'm using an Actel fuse A54SX72A, which has 2012 sequential cells and at the moment I filled it up to more than 90%. There can...

Hi to everyone, I'm using an Actel fuse A54SX72A, which has 2012 sequential cells and at the moment I filled it up to more than 90%. There can be the need more triple-redundant registers in it and I'm afraid I will have routing problems with that. Has anyone here experienced this? Can I rely on the Actel Designer backannotate to have a close-to-reality simulation? Thanks a lot -- ...


Actel Cortex M1, any info on license fee?

Started by Antti in comp.arch.fpga10 years ago 2 replies

Actel is known lying before, they namly claimed that the use of ARM7 in Actel FPGA is free, actually the FPGA with AES128 that allows the use of...

Actel is known lying before, they namly claimed that the use of ARM7 in Actel FPGA is free, actually the FPGA with AES128 that allows the use of ARM7 costs 100 USD more then FPGA without the key, and well I would not call 100USD "free" Now Actel is about to release the smaller Cortex based FPGA (eg another key for cortex-enable), again Actel claim its "Free" - I hope they are not lying thi...


help with OVL on Actel tool

Started by tullio in comp.arch.fpga7 years ago 1 reply

Hi, I am a verilog designer and I'd like to try OVL on an Actel design. I can't figure out how to use the OVL library. I downloaded it, but...

Hi, I am a verilog designer and I'd like to try OVL on an Actel design. I can't figure out how to use the OVL library. I downloaded it, but in the Actel Libero tool I can't find any way to add a path to the library. So if on my verilog code I put a OVL assertion, it will be flagged as an error by the Actel "Check HDL file" feature. Any advice ?


bandpass filter design for ACTEL FPGA

Started by mughat in comp.arch.fpga12 years ago 1 reply

Anyone have experience with designing band pass filters for ACTEL FPGAs? Tools, appnotes anything is of interest. I my project I have to make...

Anyone have experience with designing band pass filters for ACTEL FPGAs? Tools, appnotes anything is of interest. I my project I have to make some DSP on 3 audio signals (100Hz-22Khz). Planing on using the new Fusion mixed-signal FPGA from ACTEL.


Actel dropped ARM7, when comes Xilinx ARM enabled silicon?

Started by Antti in comp.arch.fpga8 years ago 5 replies

Actel has silently dropped all M7(ARM7 enabled) silicon. They have not announced this as big news, but true it is, there are no more M7 devices...

Actel has silently dropped all M7(ARM7 enabled) silicon. They have not announced this as big news, but true it is, there are no more M7 devices in product tables. Years ago when Actel announced M7 i wanted to get some of them, but Actel lied about the licensing, saying that there is no license fee, actual story was that the M7 silicon (what is plain FPGA + AES key) did cost maybe 100$ more...


Too Easy: Actel FPGA's! :)

Started by Antti in comp.arch.fpga8 years ago 4 replies

5 minutes video http://www.youtube.com/watch?v=hnmSJJOD86A from vhdl to the programming files, and programming without...

5 minutes video http://www.youtube.com/watch?v=hnmSJJOD86A from vhdl to the programming files, and programming without actel programmer using DirecC and usb-jtag cable Antti PS i messed up alter-actel in the video a few times :(


Actel FPGA corePWM IP

Started by RaulGonz in comp.arch.fpga8 years ago 3 replies

Hi, I wish to know if anyone of you out there is using an Actel FPGA board and knows how to generate PWM signal using the corePWM IP? If you...

Hi, I wish to know if anyone of you out there is using an Actel FPGA board and knows how to generate PWM signal using the corePWM IP? If you do, please let me know as i am having a hard time trying to follow the application note provided by actel on the corePWM. Thank you!


Actel FPGA programming using libero 8.1 generated SVF files

Started by Antti in comp.arch.fpga10 years ago 1 reply

Hi Since version 8.1 Actel provides SVF programming file generation for A3 FPGA's but I have problems using those SVF files: For first...

Hi Since version 8.1 Actel provides SVF programming file generation for A3 FPGA's but I have problems using those SVF files: For first testing i used Xilinx IMPACT as SVF playback engine, and I got scan data mismatch error on any actel SVF files then i used my own SVF player and got same result (JTAG port and Actel FPGA connections are ok, my own software can identify chain ok) w...


Porting Actel code

Started by Baxter in comp.arch.fpga12 years ago 7 replies

I inherited some code for the Actel fpga. The author said he downloaded the demo toolset (early version) from Actel and then reset his PC clock...

I inherited some code for the Actel fpga. The author said he downloaded the demo toolset (early version) from Actel and then reset his PC clock until he was able to finish. My understanding is that the toolchain has changed substantially since he wrote the code. I need two things: 1 - to be able to read the code/project and determine what it does 2 - to be able to revise/maintain the c...


Actel constraints?

Started by Nial Stewart in comp.arch.fpga9 years ago 6 replies

Does anyone have any pointers to a good document describing how to apply constraints to Actel FPGAs? I'm trying to transfer a design from a...

Does anyone have any pointers to a good document describing how to apply constraints to Actel FPGAs? I'm trying to transfer a design from a Cyclone II to an Actel A3P600 (Pro-Asic 3) but am having problems applying and passing IO timing constraints relative to the internal clock. Thanks for any pointers, Nial


[actel] resource usage by entity

Started by kclo4 in comp.arch.fpga6 years ago 2 replies

Hi , I am currently designing a FPGA Actel Proasci3 and I would like to know the ressource usage (ram/flipflop...) for each of module of...

Hi , I am currently designing a FPGA Actel Proasci3 and I would like to know the ressource usage (ram/flipflop...) for each of module of the project , in Altera and Xilinx they report this information easily but I don't find it in Actel Designer (we also use synplify for synthesis so it shall be fine to use synplify reporting too) Thank you for your tips! Alexis


FPGA package size chart (smallest) Xilinx holds 8th place

Started by Antti in comp.arch.fpga9 years ago 3 replies

Here it is the list as known today Package size 1. 3x4 mm 65L04 SiliconBlue 2. 4x4 mm AGL030 Actel 3. 4x5 mm 65L08 SiliconBlue 4. 5x5 mm ...

Here it is the list as known today Package size 1. 3x4 mm 65L04 SiliconBlue 2. 4x4 mm AGL030 Actel 3. 4x5 mm 65L08 SiliconBlue 4. 5x5 mm =95 AGL030 Actel =95 EPM240Z Altera 5. 5x6 mm 65L16 SiliconBlue 6. 6x6 mm =95 AGL060 Actel =95 EPM240/570 Altera =95 65L02 SiliconBlue =95 PolarPro QuickLogic 7. 7x7 mm EPM570Z Altera 8. 8x8 mm =95 A3P/IGLOO Actel ...


Trying to find some Actel A54SX16P FPGAs to purchase

Started by Joel Kolstad in comp.arch.fpga13 years ago 1 reply

Does anyone know where I might obtain some Actel A54SX16P FPGAs in the VQ100 package? Actel has exactly one distributor, and they're out of...

Does anyone know where I might obtain some Actel A54SX16P FPGAs in the VQ100 package? Actel has exactly one distributor, and they're out of stock for awhile. We've been searching the gray market some, and I figured I'd ask here. Speed grade doesn't matter, pricing isn't too important (within reason), just the package and the fact that it's the 'P' suffix (we're using it with 5V inpu...


News from Embedded World in Nurnber

Started by Antti in comp.arch.fpga12 years ago 8 replies

News from Embedded World News, Nurnberg 14.02.2006 Actel ===== Had no booth, but Actel-guy was moving around so I catched him. Actel...

News from Embedded World News, Nurnberg 14.02.2006 Actel ===== Had no booth, but Actel-guy was moving around so I catched him. Actel Fusion FPGAs: Delayed for 6 months. Do not expect Fusion silicon samples or starterkit sooner! Dont beg, dont ask - all Fusion silicon available has been allocated. This was really sad for me as I did order and pay for Actel Fusion starterkit already last ...


Experiences with Actel ProAsic3E and toolchain?

Started by Anonymous in comp.arch.fpga12 years ago 3 replies

I'm considering these parts for a new design, and the low static power and small footprint, instant-on features seem nice. In terms of...

I'm considering these parts for a new design, and the low static power and small footprint, instant-on features seem nice. In terms of performance or density, this app is not demanding at all, but we want more headroom than a CPLD gives. I haven't used Actel parts or SW for over 10 years - how have design/supply/support experiences been on ProAsic3E?? How decent are the Actel tools ...


Actel Fusion FPGAs

Started by rickman in comp.arch.fpga12 years ago 9 replies

I read a couple of threads on the Actel Fusion FPGAs from early this year saying they were delayed and not to expect them for up to 6 months. ...

I read a couple of threads on the Actel Fusion FPGAs from early this year saying they were delayed and not to expect them for up to 6 months. It is now 3 months later and I was wondering if anyone had heard anything more from Actel on these parts. I was looking at the web site for their combination Fusion and ARM core they call the M7Fusion. It is shown in two parts, the M7AFS600 with 70...


Can't get Actel tools to run on SL4.4 (RHEL 4.4)

Started by General Schvantzkoph in comp.arch.fpga10 years ago

Has anyone been able to get the Actel Linux tools to run? I wasn't able to install them on CentOS5 so booted into Scientific Linux 4.4 (a RHEL...

Has anyone been able to get the Actel Linux tools to run? I wasn't able to install them on CentOS5 so booted into Scientific Linux 4.4 (a RHEL 4.4 clone). Installation went fine in 4.4 but I haven't been able to run the tools. I'm getting, /usr/local/tools/Actel/LiberoLU80_Lin/Libero/bin/windu_scm: relocation error: /usr/local/tools/Actel/LiberoLU80_Lin/Libero/lib/libwinsock50.so: sym...


asynchronous logic on Actel Axcelerator?

Started by Adam Megacz in comp.arch.fpga13 years ago

Has anybody heard of or done an asynchronous design (delay-intolerant, isochronic fork, or logical-effort based) on Actel's...

Has anybody heard of or done an asynchronous design (delay-intolerant, isochronic fork, or logical-effort based) on Actel's Axcelerator? SRAM and Flash FPGAs have a clear bias towards synchronous designs, but it seems like Actel's antifuse offering isn't as bad for async design. Particularly encouraging is the fact that you can create a stable state element by creating feedback between t...