Actel Core PCI

Started by sarah in comp.arch.fpga15 years ago

Hi, I have a problem when implementing PCI in Acte;l APA300. Does anybody know the very datailed information about ACTEL cORE pci? Thank...

Hi, I have a problem when implementing PCI in Acte;l APA300. Does anybody know the very datailed information about ACTEL cORE pci? Thank you very much. Sarah


Actel Igloo Partial Reconfiguration

Started by Paolo Roberto Grassi in comp.arch.fpga9 years ago 1 reply

Hello everybody, someone knows if the Actel Igloo(s) devices can be partial reconfigured like xilinx devices do? It is not important if this...

Hello everybody, someone knows if the Actel Igloo(s) devices can be partial reconfigured like xilinx devices do? It is not important if this is supported by the software, I just need to know if this is theorically possible. Any idea is welcome!!! Thank you PRG


Actel CoreABC not working in Libero 8.5

Started by Antti in comp.arch.fpga10 years ago 3 replies

Hi according to the screenshot here http://www.actel.com/products/software/smartdesign/default.aspx it seems that CoreABC can be used in...

Hi according to the screenshot here http://www.actel.com/products/software/smartdesign/default.aspx it seems that CoreABC can be used in Libero, but when trying to add a CoreABC instance it asks for CoreConsole to be installed and configured. and if that is done, then it will forget some of the connections made and if that project is closed and reopened then it says that in need to upg...


Actel FUSIN chips are real !

Started by Antti in comp.arch.fpga12 years ago 1 reply

Hi Actel FUSION kit that I had ordered in DEC 2005 (was supposed to be off-the-shelf !) arrived today. Only 6 months delay. Havent have...

Hi Actel FUSION kit that I had ordered in DEC 2005 (was supposed to be off-the-shelf !) arrived today. Only 6 months delay. Havent have time to play yet, only powered the board, the Analog Digital converter in the FPGA defenetly works as analog valtage from an poti is displayed on the LED's. Antti


Actel timing constraints

Started by Niv (KP) in comp.arch.fpga12 years ago 4 replies

I need to write some timing constraints for an ProAsic device. The Designer tool doesn't seem to cater for what I need; as follows: FPGA1...

I need to write some timing constraints for an ProAsic device. The Designer tool doesn't seem to cater for what I need; as follows: FPGA1 (Xilinx) outputs data on clk rising edge & FPGA2 (my Actel) captures data on the clk falling edge (Same clock with very low skew to both devices) Similarly Actel outputs data on clk falling edge & Xilinx capture on rising edge. I have the Xilinx inpu...


Programming Actel A3P with SVF files

Started by Antti in comp.arch.fpga10 years ago 1 reply

Hi I am trying to use amontec SVF player to program Actel FPGA using the SVF files generated with Libero 8.5 and getting error on erase...

Hi I am trying to use amontec SVF player to program Actel FPGA using the SVF files generated with Libero 8.5 and getting error on erase already. the SVF seems to be executed correctly, the ID is checked the execution time is correct, but the part just doesnt get erased any hints? Antti


better choice for high-speed, multi-clock FPGA?

Started by starfire in comp.arch.fpga14 years ago

Hi all - I'm using an Actel AX250-2 (Axcelerator) in a new design which uses several phased clocks at about 250MHz. The phase relationship...

Hi all - I'm using an Actel AX250-2 (Axcelerator) in a new design which uses several phased clocks at about 250MHz. The phase relationship is important and one of the reasons for the Actel choice. They have a very fine adjustment for the PLLs and a low jitter measurement number. I tried to get the AX250-3 part but they are having trouble with the manufacture process. The -2 is ful...


Static PLL

Started by Vince in comp.arch.fpga11 years ago 4 replies

Hi all, I want to create a clock of 40MHz and 10MHz on my ACTEL ProASIC3 evaluation board, I try to use the Static PLL macro from the...

Hi all, I want to create a clock of 40MHz and 10MHz on my ACTEL ProASIC3 evaluation board, I try to use the Static PLL macro from the Libero IDE since in the documentation of ACTEL they tell us to use this macro's for best performance,... But I can't get this system working anyone has some experience with this Macro? (An example will be fine) Kind regards and thanks for the help, Vinc...


Actel Designer on Linux

Started by Neill A in comp.arch.fpga14 years ago 3 replies

Does anyone have any experience of running Actel Designer on Linux? We currently use WinXP, and have recently been informed that if we...

Does anyone have any experience of running Actel Designer on Linux? We currently use WinXP, and have recently been informed that if we used Linux, then Designer would run 10x faster. I would just like to see if anyone out there can confirm this before trying to get a machine set up with Linux. Also since I'm talking about Linux, is there any preference as to which distro is best for FPG...


help! ACTEL PROASIC PLUS clock buffer

Started by merche in comp.arch.fpga11 years ago 7 replies

Hi!, I have a big problem: I use Libero to Proasic Plus Family of Actel. My FPGA has got 4 global pin (4 GL macro), I need put a clock in a...

Hi!, I have a big problem: I use Libero to Proasic Plus Family of Actel. My FPGA has got 4 global pin (4 GL macro), I need put a clock in a global buffer but I can=B4t because I have others signals with highest fanout. what can I do? thanks ch


Adders with multiple inputs?

Started by Anonymous in comp.arch.fpga10 years ago 12 replies

Hi guys, At the moment I'm waiting to find out whether I will be using Xilinx or Actel for my project, and so I'm putting it together for both...

Hi guys, At the moment I'm waiting to find out whether I will be using Xilinx or Actel for my project, and so I'm putting it together for both just in case. In the Actel IP cores, there is an array adder which allows a good number of inputs, and there's some optional pipelining. I figure it's sufficient to just drop this in and wire up as many inputs as I need. Xilinx IP cores seem to h...


CoreTimer programming in Actel SoftConsole

Started by self in comp.arch.fpga8 years ago

Hello, I am trying to measure the execution time of some code using a CoreTimer block connected to a Cortex-M1 processor design in an...

Hello, I am trying to measure the execution time of some code using a CoreTimer block connected to a Cortex-M1 processor design in an Actel Fusion part. My problem is that TMR_current_value() always returns 0. I am trying to run in TMR_ONE_SHOT_MODE but I have also tried continuous mode but no change. I have also double checked that the CoreTimer block is attached to the APB bus and ...


Wanted Actel ProAsic RAM VHDL models

Started by scd in comp.arch.fpga13 years ago 1 reply

Hi, I've tried inferring RAMs, but it doesn't seem to work well, so I want to just instantiate the Actel RAM primitives. Does anyone have a...

Hi, I've tried inferring RAMs, but it doesn't seem to work well, so I want to just instantiate the Actel RAM primitives. Does anyone have a 4kx9 or 512x18 RAM model that uses instantiated ProAsic RAM primitives? Thanks, Scott scd -at- teleport -dot- com


FPGA ARM IP Core

Started by Antti Lukats in comp.arch.fpga13 years ago 3 replies

Hi Group, from "Actel is bringing ARM7 to the masses with no upfront licensing fees and no royalties" - this is totally nonsense! I have...

Hi Group, from "Actel is bringing ARM7 to the masses with no upfront licensing fees and no royalties" - this is totally nonsense! I have been trying to buy 1 sample ARM7 ready device from Actel for some time now, calling them and asking all over again. They claim that ARM ready PA3 silicon is available, but pricing? As soon as I try to ask the prices they will start to explain the li...


Cortex-M1 in Actel in strait VHDL?

Started by self in comp.arch.fpga8 years ago 2 replies

Hello All, I have a requirement to build a SOC design with two Arm cores along with some standard and custom peripherals. The Actel...

Hello All, I have a requirement to build a SOC design with two Arm cores along with some standard and custom peripherals. The Actel Cortex-M1 enabled FPGA's appear to be ideal for my application because the licensing fee is included in the price of the processor. I have started playing around with the Libero tools to see how processor development is done with them. The Libero environme...


ABC - Actel's PicoBlaze :) - anybody success with coreconsole?

Started by Antti in comp.arch.fpga12 years ago 1 reply

Hi new version of actel coreconsole includes CoreABC - a tiny Fpga SoftCore with APB interface for peripherals, but I have trouble creating a...

Hi new version of actel coreconsole includes CoreABC - a tiny Fpga SoftCore with APB interface for peripherals, but I have trouble creating a SoC, i wonder if any one has worked it out ? hm.. eh, I tried to connect Fusion on chip used Flash blocks to ABC, maybe this is not supported and was the reason for problem. Still if anyone has experience with ABC, would be nice to hear:) Antti ...


pre-synthezis simulation in ModelSim for Actel

Started by Anonymous in comp.arch.fpga12 years ago 4 replies

I'm using Model for Actel. When performing pre-synthesis simulation in ModelSim, I observe 'unknown' signals in design. However, these signals...

I'm using Model for Actel. When performing pre-synthesis simulation in ModelSim, I observe 'unknown' signals in design. However, these signals are defined in simulation which I made in other simulator. Thanks for help


System gates: Altera <-> Actel

Started by Nagaraj in comp.arch.fpga9 years ago 2 replies

Dear all, I'm looking for the equivalent system gate figures (like in Actel Igloo series) of Altera Cyclone II devices. Specifically,...

Dear all, I'm looking for the equivalent system gate figures (like in Actel Igloo series) of Altera Cyclone II devices. Specifically, an equivalent for the EP2C50 in the Igloo series. Any suggestion / link is highly appreciated. Nagaraj


use lattice and actel synplify together...

Started by Jedi in comp.arch.fpga13 years ago 1 reply

Is it possible to have for each tool an own license file path set? Lattice ispLever Base with synplify bites Actel Libero Platinum with...

Is it possible to have for each tool an own license file path set? Lattice ispLever Base with synplify bites Actel Libero Platinum with synplify since each version of synplify doesn't like the other license file... thx in advance jedi


About Unstable Operation of ACTEL(A3P1000)....

Started by kypilop in comp.arch.fpga12 years ago 7 replies

Hi.. I can't understand about this situation.... I use same source(VHDL), same program tool(Libero), same device(A3P1000) and same...

Hi.. I can't understand about this situation.... I use same source(VHDL), same program tool(Libero), same device(A3P1000) and same programmer(FlashPro3)....But the device operation is not regular.... I test some functions using StartKit from Actel Co. Many times, parts of function are un-operation.... The un-operated functions are not fixed !!! Malfunctions are irregular......................