Altera simulation models performance

Started by mikel in comp.arch.fpga13 years ago 2 replies

Hi Is there a way to increase performance of Altera functional simulation models? Specifically, I am using FFT core in our project and this...

Hi Is there a way to increase performance of Altera functional simulation models? Specifically, I am using FFT core in our project and this is the bottleneck of simulation speed, which I am not surprised to see, given that VHO model is hundred of thousand lines of technology mapped code consisting of Altera library primitives. Using Verilog *.VO does not give much improvement. Moreover, F...


configuring an Altera Cyclone 3

Started by John Larkin in comp.arch.fpga10 years ago 7 replies

Hi, I have an FPGA design that works from JTAG, and now I want to burn a serial flash chip so it will configure itself at powerup. The...

Hi, I have an FPGA design that works from JTAG, and now I want to burn a serial flash chip so it will configure itself at powerup. The mode pins should be right for serial self-load, and we'll be using a standard serial flash chip, an M25P16. We have a B&K USB flash burner. I've read the Altera lit and it's not entirely clear to me, so I'd appreciate some help. What Altera file fo...


Altera "my support" :-(

Started by Rotem Gazit in comp.arch.fpga18 years ago 6 replies

We have been working with Xilinx parts for the past 4 years. Whenever I had problem the local FAE couldn't solve I used the Xilinx WEB case...

We have been working with Xilinx parts for the past 4 years. Whenever I had problem the local FAE couldn't solve I used the Xilinx WEB case system. I always got very fast and professional response, usually within the same working day. Recently we decided to use Altera Cyclone part in a new design. When we ran into problems I opened a web case using "Altera's my support". After two days o...


File format *.eqn in Altera IDE

Started by Markus Koechy in comp.arch.fpga17 years ago 2 replies

Hi, Altera Quartus-II produces *.eqn files. Does anyone know where I can find a detailed description of this fileformat? Thanks, Markus.

Hi, Altera Quartus-II produces *.eqn files. Does anyone know where I can find a detailed description of this fileformat? Thanks, Markus.


Altera winner?

Started by Jerry in comp.arch.fpga17 years ago 8 replies

Does anyone know who won the camera from Altera on that Cyclone 2 web presentation?

Does anyone know who won the camera from Altera on that Cyclone 2 web presentation?


Altera Cyclone II and Cyclone III "distributed" RAM?

Started by Ioiod in comp.arch.fpga14 years ago 3 replies

I looked on Altera's website, but I could not find any description on how distributed (LUT-based) RAM works on the CYclone II/III family. FOr...

I looked on Altera's website, but I could not find any description on how distributed (LUT-based) RAM works on the CYclone II/III family. FOr the Stratix III, I see Altera called this feature "M-LAB." Am I missing something obvious? Or do the Cyclone family simply not supported distributed RAM?


altera DDR core simulation with NCSim

Started by Jan De Ceuster in comp.arch.fpga17 years ago 6 replies

Quite a simple question: how to simulate the DDR-SDRAM core from Altera in NCSim. I just can 't figure it out though Altera *claims* to support...

Quite a simple question: how to simulate the DDR-SDRAM core from Altera in NCSim. I just can 't figure it out though Altera *claims* to support NCSim. To me it looks like their development chain is realy ModelSim/Quartus only... The things I've tried: * simulate netlist from core (yes I've got a license) : doesnt' work due to errors when trying to compile the thing. * dump a "functional...


boundary scan of altera epm570F

Started by colin in comp.arch.fpga16 years ago 3 replies

Guys I'm going home with a problem unsolved. After an ALTERA EPM570F has been programmed can it still be boundary scanned using the...

Guys I'm going home with a problem unsolved. After an ALTERA EPM570F has been programmed can it still be boundary scanned using the original BSDL file or does the fact that IO pins are now hard wired as Input or Output mean that they can only be scanned as Inputs or Outputs. (nneding the BSDL to be changed). I have spent an hour on the ALTERA website and it is not at all clear. In som...


Altera webpack for Linux?

Started by radarman in comp.arch.fpga14 years ago 3 replies

I noticed that the Xilinx webpack version of ISE now runs in Linux. I seem to recall in the past that the webpack was a Windows only tool, so...

I noticed that the Xilinx webpack version of ISE now runs in Linux. I seem to recall in the past that the webpack was a Windows only tool, so this seems like a signficant shift. Does anyone know if Altera has any plans to release a Quartus webpack for Linux? I still prefer Altera devices for my hobby work even though my current employer is 100% Xilinx. However, I'm looking down the barrel ...


Altera unable to respond

Started by ALuPin in comp.arch.fpga17 years ago

Hi, is it possible to simulate under Modelsim (OEM Altera 5.7e) a testbench (without any timing information) which includes a module with an...

Hi, is it possible to simulate under Modelsim (OEM Altera 5.7e) a testbench (without any timing information) which includes a module with an SDF file? (The SDF file is attached under ---> Simulate --> SDF ----> Add SDF file FILENAME_vhd.sdo + Apply to region u1 (instantiation name of the module in the testbench) I would appreciate your help because Altera seems not to be able to r


Altera subscriptions deleted?

Started by Jedi in comp.arch.fpga17 years ago 2 replies

What happended to the susbcription information if you log into your "mySupport" page at Altera? Altera_ID and software subscription...

What happended to the susbcription information if you log into your "mySupport" page at Altera? Altera_ID and software subscription informations are gone! rick


Low-level FPGA programming?

Started by Anonymous in comp.arch.fpga14 years ago 9 replies

Hi. It is possible to have a format of .pof/.sof files from Altera, thus, to decompile some ready projects and try to make our own,...

Hi. It is possible to have a format of .pof/.sof files from Altera, thus, to decompile some ready projects and try to make our own, omitting Altera software tools?


XIlinx 7.1i ISE problem with Spartan 3e design

Started by radarman in comp.arch.fpga15 years ago 2 replies

Guys/Gals, I am primarily an Altera developer at work, so I have a lot more experience with Quartus than ISE. (our site develops with both...

Guys/Gals, I am primarily an Altera developer at work, so I have a lot more experience with Quartus than ISE. (our site develops with both Altera and Xilinx designs, but most of my projects have involved Altera devices) However, as the proud recipient of a Spartan 3E sample pack board, I decided to give it a go. I am using the tool chain at work, because our site has the 7.1 EDK and ChipS...


Can someone give me some pointers on using ibis models?

Started by Teece in comp.arch.fpga15 years ago 3 replies

Hi, I have been doing designs, digital and analog, for over 20 years, without making use of ibis data, but I think that is about to end. I...

Hi, I have been doing designs, digital and analog, for over 20 years, without making use of ibis data, but I think that is about to end. I was doing a design with one of the newer Altera BGA's and could not find the ususal "rise time", "fall time" data, so I inquired to Altera. Altera told me that they provide ibis models for more cases than I could count but that the "old style" specifi...


Altera Quartus 4.2 Service Pack 1 fails to install

Started by Jedi in comp.arch.fpga17 years ago 7 replies

Apparently Altera was too quick in releasing SP1. It is just too stupid to find any previous 4.2 installation. rick

Apparently Altera was too quick in releasing SP1. It is just too stupid to find any previous 4.2 installation. rick


Altera Stratix kit PCI to DDR reference design

Started by E. van Putten in comp.arch.fpga17 years ago

Hi everbody, The Stratix PCI kit is a 32/64-bits PCI board from Altera with 256 MB of DDR SDRAM (SO-DIMM). This kit includes a nice...

Hi everbody, The Stratix PCI kit is a 32/64-bits PCI board from Altera with 256 MB of DDR SDRAM (SO-DIMM). This kit includes a nice reference design that has a PCI to DDR bridge. We would like to use this design as a starting point for our own designs. Unfortunately this design only works with the old Quartus II v2.1 and the v1.2.1 SDRAM IP Megacore from Altera. Importing the older ...


Altera Stratix kit PCI to DDR reference design

Started by E. van Putten in comp.arch.fpga17 years ago

Hi everbody, The Stratix PCI kit is a 32/64-bits PCI board from Altera with 256 MB of DDR SDRAM (SO-DIMM). This kit includes a nice reference...

Hi everbody, The Stratix PCI kit is a 32/64-bits PCI board from Altera with 256 MB of DDR SDRAM (SO-DIMM). This kit includes a nice reference design that has a PCI to DDR bridge. We would like to use this design as a starting point for our own designs. Unfortunately this design only works with the old Quartus II v2.1 and the v1.2.1 SDRAM IP Megacore from Altera. Importing the older pr...


altera's USB byteblaster cable: anyone has the mindford one?

Started by Rodo in comp.arch.fpga14 years ago 2 replies

Hi all, I haven't used any altera stuff for a while. Last time I used the MAX3000A, I built the parallel port byteblaster cable from the info...

Hi all, I haven't used any altera stuff for a while. Last time I used the MAX3000A, I built the parallel port byteblaster cable from the info on the altera's web site. This is the original not the improved one they have now. It was like $10 in parts and did the trick. I still have it and works but my new laptop doesn't have a parallel port. The USB stuff is ridiculously priced ($300 a...


Programming Altera Config Device

Started by Gary Pace in comp.arch.fpga17 years ago 2 replies

We have a number of PCB's with Altera Cyclone/Config device systems. In R&D we use Quartus to program this. For production, we have a bed of...

We have a number of PCB's with Altera Cyclone/Config device systems. In R&D we use Quartus to program this. For production, we have a bed of nails based ATE system, using LabView. We want to program the config. device automatically. Has anyone done this ? Does Altera produce a .dll or .ocx version of the programming tools ? Can the programmer be run as a WIN32 console app. (ie from...


suggestion for choosing the right FPGA for gigabit transciever

Started by vasile in comp.arch.fpga14 years ago 5 replies

Hi, I need to chose between the Altera Stratix II GX or Stratix III GX and some Xilinx Virtex5 FPGA for an implementation of gigabit...

Hi, I need to chose between the Altera Stratix II GX or Stratix III GX and some Xilinx Virtex5 FPGA for an implementation of gigabit interface into a multi DSP system. Could you suggest pro and cons between Altera and Xilinx (or maybe others) for such design ? If I'm trying to compare Altera with Xilinx FPGA based on those websites, both are telling is better than the other. Maybe you ...